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    Accessing encoded blocks of data
    1.
    发明授权
    Accessing encoded blocks of data 有权

    公开(公告)号：US11954028B2

    公开(公告)日：2024-04-09

    申请号：US17657498

    申请日：2022-03-31

    Applicant: Arm Limited

    Inventor： Edvard Fielding ,  Jian Wang ,  Jakob Axel Fries ,  Carmelo Giliberto

    IPC: G06F12/06

    CPC classification number: G06F12/0646 ,  G06F2212/40

    Abstract: There is disclosed a method of storing an encoded block of data in memory comprising encoding a block of data elements and determining a memory location (26) at which the encoded block of data is to be stored. The memory location (26) at which the encoded block of data is stored is then indicated in a header (406) for the encoded block of data by including in the header a memory address value (407) together with a modifier value (500) representing a modifier that is to be applied to the memory address value (407) when determining the memory location (26). When the encoded block of data is to be retrieved, the header (406) is read and processed to determine the memory location (26).

    Selective write-once-memory encoding in a flash based disk cache memory
    4.
    发明授权
    Selective write-once-memory encoding in a flash based disk cache memory 有权
    基于闪存的磁盘缓存内存中的选择性一次写入内存编码

    公开(公告)号：US08914570B2

    公开(公告)日：2014-12-16

    申请号：US13464084

    申请日：2012-05-04

    Applicant: Ganesh Balakrishnan ,  Anil Krishna

    Inventor： Ganesh Balakrishnan ,  Anil Krishna

    IPC: G06F12/00

    CPC classification number: G06F12/0866 ,  G06F12/0246 ,  G06F2212/222 ,  G06F2212/40 ,  Y02D10/13

    Abstract: In a method for storing data in a flash memory array, the flash memory array includes a plurality of physical pages. The method includes receiving a request to perform a data access operation through a communication bus. The request includes data and a logical page address. The method further includes allocating one or more physical pages of the flash memory array to perform the data access operation. The method further includes, based on a historical usage data of the flash memory array, selectively encoding the data contained in the logical page into the one or more physical pages.

    Abstract translation: 在将数据存储在闪存阵列中的方法中，闪存阵列包括多个物理页。 该方法包括通过通信总线接收执行数据访问操作的请求。 该请求包括数据和逻辑页面地址。 该方法还包括分配闪存阵列的一个或多个物理页面以执行数据访问操作。 该方法还包括基于闪速存储器阵列的历史使用数据，选择性地将包含在逻辑页面中的数据编码到一个或多个物理页面中。

    DENSELY STORED STRINGS
    7.
    发明申请
    DENSELY STORED STRINGS 有权

    公开(公告)号：US20170083300A1

    公开(公告)日：2017-03-23

    申请号：US14863189

    申请日：2015-09-23

    Applicant: Oracle International Corporation

    Inventor： Charles J. Hunt ,  Aleksey Shipilev ,  Brent A. Christian ,  Xueming Shen ,  Roger Stephen Riggs ,  Vladimir Kozlov

    IPC: G06F9/45 ,  G06F12/02

    CPC classification number: G06F8/4434 ,  G06F12/0223 ,  G06F12/023 ,  G06F2212/40

    Abstract: The disclosed embodiments provide a system for densely storing strings within the memory of a software program. During operation, the system receives a set of characters to be stored in a string, wherein each character is encoded using a multi-byte public encoding. The system then stores the set of characters in the string at least in part by performing the following steps. The system determines whether every character of the set can be encoded using a first private encoding that consumes less space per character than the multi-byte public encoding. Responsive to determining that every character of the set can be encoded using the first private encoding, the system stores a particular value associated with the first private encoding in a particular field of the string. The system then stores the set of characters in the string in the first private encoding.

    Dynamic memory address encoding
    9.
    发明授权
    Dynamic memory address encoding 有权

    公开(公告)号：US11681622B2

    公开(公告)日：2023-06-20

    申请号：US17551107

    申请日：2021-12-14

    Applicant: Pony AI Inc.

    Inventor： Yubo Zhang ,  Pingfan Meng

    IPC: G06F12/0811 ,  G06F12/0846 ,  G06F12/1045 ,  G06F12/02

    CPC classification number: G06F12/0811 ,  G06F12/0292 ,  G06F12/0851 ,  G06F12/1045 ,  G06F2212/40

    Abstract: Described herein is a memory architecture that is configured to dynamically determine an address encoding to use to encode multi-dimensional data such as multi-coordinate data in a manner that provides a coordinate bias corresponding to a current memory access pattern. The address encoding may be dynamically generated in response to receiving a memory access request or may be selected from a set of preconfigured address encodings. The dynamically generated or selected address encoding may apply an interleaving technique to bit representations of coordinate values to obtain an encoded memory address. The interleaving technique may interleave a greater number of bits from the bit representation corresponding to the coordinate direction in which a coordinate bias is desired than from bit representations corresponding to other coordinate directions.

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