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公开(公告)号:US20200168717A1
公开(公告)日:2020-05-28
申请号:US16780637
申请日:2020-02-03
申请人: SK hynix Inc.
发明人: Beom-Yong KIM
摘要: A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.
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公开(公告)号:US20200020780A1
公开(公告)日:2020-01-16
申请号:US16233582
申请日:2018-12-27
申请人: SK hynix Inc.
发明人: Beom-Yong KIM
摘要: A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.
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公开(公告)号:US20180269211A1
公开(公告)日:2018-09-20
申请号:US15835629
申请日:2017-12-08
申请人: SK hynix Inc.
发明人: Beom-Yong KIM , Hun LEE , Deok-Sin KIL
IPC分类号: H01L27/108 , H01L21/02 , H01L49/02 , H01L21/311
CPC分类号: H01L27/10852 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02186 , H01L21/02189 , H01L21/022 , H01L21/02244 , H01L21/02252 , H01L21/02304 , H01L21/31111 , H01L27/10814 , H01L27/10823 , H01L28/91
摘要: A method for fabricating semiconductor device includes: forming a bottom electrode of a high aspect ratio; forming an interface layer by sequentially performing a first plasma process and a second plasma process onto a surface of the bottom electrode; forming a dielectric layer over the interface layer; and forming a top electrode over the dielectric layer.
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公开(公告)号:US20160181320A1
公开(公告)日:2016-06-23
申请号:US14696334
申请日:2015-04-24
申请人: SK Hynix Inc.
发明人: Beom-Yong KIM
CPC分类号: H01L45/1253 , G11C13/0002 , G11C2213/35 , G11C2213/52 , G11C2213/77 , H01L27/2409 , H01L27/2436 , H01L45/04
摘要: An electronic device includes a memory device that includes a switching device having an improved switching property and reliability. The semiconductor memory includes a first carbon electrode; a second carbon electrode; a switching layer provided between the first carbon electrode and the second carbon electrode; a third carbon electrode; and a variable resistance layer including nitride and provided between the second carbon electrode and the third carbon electrode.
摘要翻译: 电子装置包括具有改进的开关特性和可靠性的开关装置的存储装置。 半导体存储器包括第一碳电极; 第二碳电极; 设置在所述第一碳电极和所述第二碳电极之间的开关层; 第三碳电极; 以及包括氮化物并设置在第二碳电极和第三碳电极之间的可变电阻层。
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公开(公告)号:US20150138872A1
公开(公告)日:2015-05-21
申请号:US14249251
申请日:2014-04-09
申请人: SK HYNIX INC.
发明人: Beom-Yong KIM
CPC分类号: G11C13/0007 , G11C13/0021 , G11C2213/31 , G11C2213/33 , G11C2213/77 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/147
摘要: An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes first lines extending along a first direction; second lines extending along a second direction that intersects with the first direction; a silicon-added metal oxide layer disposed in each intersection region of the first lines and the second lines; a metal oxide layer that is disposed alternately with the silicon-added metal oxide layer in the first direction and that is disposed in a region between two adjacent second lines and over a corresponding one of the first lines over which the silicon-added metal oxide layer is disposed; and a silicon oxide layer that is disposed alternately with the silicon-added metal oxide layer in the second direction and that is disposed in a region between two first lines and under a corresponding one of the second lines under which the silicon-added metal oxide layer is disposed.
摘要翻译: 电子设备包括半导体存储单元。 半导体存储单元包括沿着第一方向延伸的第一线; 沿着与第一方向相交的第二方向延伸的第二线; 设置在第一线和第二线的每个交叉区域中的添加有硅的金属氧化物层; 金属氧化物层,其在第一方向上与添加了硅的金属氧化物层交替设置并且设置在两个相邻的第二线之间的区域中,并且在相应的第一线之上,添加有硅的金属氧化物层 被处置 以及氧化硅层,其与所述添加硅的金属氧化物层沿第二方向交替布置,并且设置在两个第一线之间的区域中,并且在相应的一条第二线下方,所述添加了硅的金属氧化物层 被处置。
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公开(公告)号:US20190165087A1
公开(公告)日:2019-05-30
申请号:US16002866
申请日:2018-06-07
申请人: SK hynix Inc.
发明人: Beom-Yong KIM , Deok-Sin KIL , Hee-Young JEON
CPC分类号: H01L28/60 , H01G4/005 , H01G4/1263
摘要: A method for fabricating a capacitor includes: forming a bottom electrode; forming a dielectric layer on the bottom electrode; forming a metal oxide layer including a metal having a high electronegativity on the dielectric layer; forming a sacrificial layer on the metal oxide layer to reduce the metal oxide layer to a metal layer; and forming a top electrode on the sacrificial layer to convert the reduced metal layer into a high work function interface layer.
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公开(公告)号:US20140299830A1
公开(公告)日:2014-10-09
申请号:US13945834
申请日:2013-07-18
申请人: SK HYNIX INC.
发明人: Beom-Yong KIM
IPC分类号: H01L45/00
CPC分类号: H01L45/08 , G11C13/0002 , G11C2213/30 , H01L27/2481 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/1658
摘要: A method for fabricating a semiconductor device includes forming an impurity layer over a first conductive layer; forming a first metal oxide layer over the impurity layer, wherein the first metal oxide layer includes oxygen at a lower ratio than a stoichiometric ratio; diffusing an impurity from the impurity layer into the first metal oxide layer to form a first doped metal oxide layer; forming a second metal oxide layer over the first doped metal oxide layer; and forming a second conductive layer over the second metal oxide layer.
摘要翻译: 一种制造半导体器件的方法包括在第一导电层上形成杂质层; 在所述杂质层上形成第一金属氧化物层,其中所述第一金属氧化物层包括比化学计量比低的氧; 将杂质从杂质层扩散到第一金属氧化物层中以形成第一掺杂金属氧化物层; 在所述第一掺杂金属氧化物层上形成第二金属氧化物层; 以及在所述第二金属氧化物层上形成第二导电层。
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公开(公告)号:US20130221425A1
公开(公告)日:2013-08-29
申请号:US13844870
申请日:2013-03-16
申请人: SK HYNIX INC.
发明人: Beom-Yong KIM
IPC分类号: H01L29/788
CPC分类号: H01L29/7889 , H01L27/11578 , H01L27/11582 , H01L29/40114 , H01L29/513 , H01L29/518 , H01L29/66666 , H01L29/66825 , H01L29/7827 , H01L29/7926
摘要: A nonvolatile memory device includes a plurality of interlayer dielectric layers and conductive layers for gate electrodes alternately stacked over a substrate, a channel trench passing through the interlayer dielectric layers and the conductive layers and exposing the substrate, a charge blocking layer and a charge trap or charge storage layer formed on sidewalls of the trench, a coupling prevention layer formed at the surface of the charge trap or charge storage layer, and a tunnel insulation layer formed over the coupling prevention layer.
摘要翻译: 非易失性存储器件包括多个层间电介质层和用于交替层叠在衬底上的栅电极的导电层,通过层间电介质层和导电层的通道沟槽和暴露衬底,电荷阻挡层和电荷阱或 形成在沟槽的侧壁上的电荷存储层,形成在电荷阱或电荷存储层的表面处的耦合防止层,以及形成在耦合防止层上的隧道绝缘层。
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公开(公告)号:US20160118442A1
公开(公告)日:2016-04-28
申请号:US14662198
申请日:2015-03-18
申请人: SK hynix Inc.
发明人: Jong-Gi KIM , Ki-Jeung LEE , Beom-Yong KIM
CPC分类号: H01L27/2427 , G06F12/0802 , G06F13/1663 , G06F13/1673 , G06F2212/40 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/141 , H01L45/146 , H01L45/147 , H01L45/16
摘要: Provided is an electronic device including a switching element, wherein the switching element may include a first electrode, a second electrode, a switching layer interposed between the first and second electrodes, and a first amorphous semiconductor layer interposed between the first electrode and the switching layer.
摘要翻译: 提供一种包括开关元件的电子设备,其中开关元件可以包括第一电极,第二电极,插入在第一和第二电极之间的开关层,以及介于第一电极和开关层之间的第一非晶半导体层 。
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公开(公告)号:US20150340608A1
公开(公告)日:2015-11-26
申请号:US14817031
申请日:2015-08-03
申请人: SK hynix Inc.
发明人: Beom-Yong KIM , Kee-Jeung LEE , Wan-Gee KIM , Hyo-June KIM
IPC分类号: H01L45/00
CPC分类号: H01L45/085 , G11C13/0004 , G11C13/0007 , G11C2213/55 , H01L27/2463 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/146 , H01L45/147
摘要: A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers.
摘要翻译: 半导体器件包括第一导电层,与第一导电层间隔开的第二导电层,插入在第一和第二导电层之间的可变电阻层,以及设置在可变电阻层的侧表面上的杂质掺杂层。 可变电阻层具有比第一和第二导电层更小的宽度。
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