公开(公告)号：US20230215807A1

公开(公告)日：2023-07-06

申请号：US18094866

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Jiun LIU ,  Chen-Yuan KAO ,  Hung-Wen SU ,  Ming-Hsing TSAI ,  Syun-Ming JANG

IPC: H01L23/532 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/3105 ,  H01L21/288 ,  H01L21/311

CPC classification number: H01L23/53238 ,  H01L21/32133 ,  H01L21/76852 ,  H01L21/76834 ,  H01L23/528 ,  H01L21/76837 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/31053 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76877 ,  H01L21/2885 ,  H01L21/288 ,  H01L21/76885 ,  H01L21/76873 ,  H01L21/31111 ,  H01L23/522 ,  H01L2924/0002

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

公开(公告)号：US20190287851A1

公开(公告)日：2019-09-19

申请号：US15920727

申请日：2018-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen CHEN ,  Chia-Han LAI ,  Chih-Wei CHANG ,  Mei-Hui FU ,  Ming-Hsing TSAI ,  Wei-Jung LIN ,  Yu Shih WANG ,  Ya-Yi CHENG ,  I-Li CHEN

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/285 ,  H01L21/3213

Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.

公开(公告)号：US20170200800A1

公开(公告)日：2017-07-13

申请号：US14990009

申请日：2016-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Ping LIU ,  Hung-Chang HSU ,  Hung-Wen SU ,  Ming-Hsing TSAI ,  Rueijer LIN ,  Sheng-Hsuan LIN ,  Ya-Lien LEE ,  Yen-Shou KAO

IPC: H01L29/45 ,  H01L21/311 ,  H01L29/51 ,  H01L21/768

CPC classification number: H01L29/456 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76832 ,  H01L21/76846 ,  H01L21/76856 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a substrate. The method includes removing a first portion of the dielectric layer to form a first hole in the dielectric layer. A second portion of the dielectric layer is under the first hole. The method includes forming a first protection layer over the gate stack and the spacer layer. The method includes forming a second protection layer over the first protection layer. The second protection layer includes a metal compound material, and the first protection layer and the second protection layer includes a same metal element. The method includes removing the second portion of the dielectric layer to form a through hole. The method includes forming a conductive contact structure in the through hole.

公开(公告)号：US20170133324A1

公开(公告)日：2017-05-11

申请号：US15401470

申请日：2017-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jiun LIU ,  Chen-Yuan KAO ,  Hung-Wen SU ,  Ming-Hsing TSAI ,  Syun-Ming JANG

IPC: H01L23/532 ,  H01L21/288 ,  H01L23/522 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

公开(公告)号：US20170110324A1

公开(公告)日：2017-04-20

申请号：US15192570

申请日：2016-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen TSAI ,  Hsin-Yi LEE ,  Chung-Chiang WU ,  Da-Yuan LEE ,  Weng CHANG ,  Ming-Hsing TSAI

IPC: H01L21/28 ,  C23C16/455

CPC classification number: H01L21/28105 ,  C23C14/58 ,  C23C14/5846 ,  C23C14/5873 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/02697 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/76838 ,  H01L21/76886

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.

公开(公告)号：US20250066899A1

公开(公告)日：2025-02-27

申请号：US18454702

申请日：2023-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yen LIAO ,  I. LEE ,  Shu-Lan CHANG ,  Sheng-Hsuan LIN ,  Feng-Yu CHANG ,  Wei-Jung LIN ,  Chun-I TSAI ,  Chih-Chien CHI ,  Ming-Hsing TSAI ,  Pei Shan CHANG ,  Chih-Wei CHANG

IPC: C23C14/04 ,  C23C14/34 ,  C23C14/50 ,  C23C14/54 ,  C23C14/58

Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.

公开(公告)号：US20200020583A1

公开(公告)日：2020-01-16

申请号：US16034843

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiang CHAO ,  Min-Hsiu HUNG ,  Chun-Wen NIEH ,  Ya-Huei LI ,  Yu-Hsiang LIAO ,  Li-Wei CHU ,  Kan-Ju LIN ,  Kuan-Yu YEH ,  Chi-Hung CHUANG ,  Chih-Wei CHANG ,  Ching-Hwanq SU ,  Hung-Yi HUANG ,  Ming-Hsing TSAI

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/45 ,  H01L23/535 ,  H01L29/66 ,  H01L21/285 ,  H01L21/265 ,  H01L21/324

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.

公开(公告)号：US20190273147A1

公开(公告)日：2019-09-05

申请号：US15909838

申请日：2018-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wen CHENG ,  Cheng-Tung LIN ,  Chih-Wei CHANG ,  Hong-Mao LEE ,  Ming-Hsing TSAI ,  Sheng-Hsuan LIN ,  Wei-Jung LIN ,  Yan-Ming TSAI ,  Yu-Shiuan WANG ,  Hung-Hsu CHEN ,  Wei-Yip LOH ,  Ya-Yi CHENG

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L21/326 ,  H01L29/78

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

公开(公告)号：US20190164823A1

公开(公告)日：2019-05-30

申请号：US15880448

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih WANG ,  Chun-I TSAI ,  Shian Wei MAO ,  Ken-Yu CHANG ,  Ming-Hsing TSAI ,  Wei-Jung LIN

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/3213

CPC classification number: H01L21/76847 ,  H01L21/32134 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.

公开(公告)号：US20150371943A1

公开(公告)日：2015-12-24

申请号：US14837458

申请日：2015-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Hung-Wen SU ,  Shih-Wei CHOU ,  Ming-Hsing TSAI

IPC: H01L23/528 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer includes metal ions.

Abstract translation: 提供了可以减少或甚至防止对其中低k电介质层的损坏的用于形成其的半导体器件及其制造方法。 提供了一种半导体器件，包括衬底。 其中具有至少一个导电特征的电介质层覆盖在衬底上。 绝缘帽层覆盖邻近导电特征的低k电介质层的顶表面，其中绝缘帽层包括金属离子。