公开(公告)号：US20200020583A1

公开(公告)日：2020-01-16

申请号：US16034843

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiang CHAO ,  Min-Hsiu HUNG ,  Chun-Wen NIEH ,  Ya-Huei LI ,  Yu-Hsiang LIAO ,  Li-Wei CHU ,  Kan-Ju LIN ,  Kuan-Yu YEH ,  Chi-Hung CHUANG ,  Chih-Wei CHANG ,  Ching-Hwanq SU ,  Hung-Yi HUANG ,  Ming-Hsing TSAI

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/45 ,  H01L23/535 ,  H01L29/66 ,  H01L21/285 ,  H01L21/265 ,  H01L21/324

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.

公开(公告)号：US20190097012A1

公开(公告)日：2019-03-28

申请号：US15964352

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu HUNG ,  Yi-Hsiang CHAO ,  Kuan-Yu YEH ,  Kan-Ju LIN ,  Chun-Wen NIEH ,  Huang-Yi HUANG ,  Chih-Wei CHANG ,  Ching-Hwanq SU

IPC: H01L29/45 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/3205

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate including a conductive region made of silicon, germanium or a combination thereof. The method also includes forming an insulating layer over the semiconductor substrate and forming an opening in the insulating layer to expose the conductive region. The method also includes performing a deposition process to form a metal layer over a sidewall and a bottom of the opening, so that a metal silicide or germanide layer is formed on the exposed conductive region by the deposition process. The method also includes performing a first in-situ etching process to etch at least a portion of the metal layer and forming a fill metal material layer in the opening.

公开(公告)号：US20230411242A1

公开(公告)日：2023-12-21

申请号：US17807476

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kan-Ju LIN ,  Lin-Yu HUANG ,  Min-Hsuan LU ,  Wei-Yip LOH ,  Hong-Mao LEE ,  Harry CHIEN

IPC: H01L23/48 ,  H01L29/417 ,  H01L21/768 ,  H01L29/40

CPC classification number: H01L23/481 ,  H01L29/41733 ,  H01L21/76898 ,  H01L29/401 ,  H01L29/45

Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.

公开(公告)号：US20230068965A1

公开(公告)日：2023-03-02

申请号：US17459494

申请日：2021-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hung CHU ,  Shuen-Shin LIANG ,  Hsu-Kai CHANG ,  Tzu Pei CHEN ,  Kan-Ju LIN ,  Chien CHANG ,  Hung-Yi HUANG ,  Sung-Li WANG

IPC: H01L29/45 ,  H01L29/417 ,  H01L23/532 ,  H01L29/40 ,  H01L21/311 ,  H01L21/8234

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.

公开(公告)号：US20200335597A1

公开(公告)日：2020-10-22

申请号：US16914638

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu HUNG ,  Yi-Hsiang CHAO ,  Kuan-Yu YEH ,  Kan-Ju LIN ,  Chun-Wen NIEH ,  Huang-Yi HUANG ,  Chih-Wei CHANG ,  Ching-Hwanq SU

IPC: H01L29/45 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/321

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed over the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below the gate structure. The semiconductor device structure further includes two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. The first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall. The gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.