公开(公告)号：US20230411242A1

公开(公告)日：2023-12-21

申请号：US17807476

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kan-Ju LIN ,  Lin-Yu HUANG ,  Min-Hsuan LU ,  Wei-Yip LOH ,  Hong-Mao LEE ,  Harry CHIEN

IPC: H01L23/48 ,  H01L29/417 ,  H01L21/768 ,  H01L29/40

CPC classification number: H01L23/481 ,  H01L29/41733 ,  H01L21/76898 ,  H01L29/401 ,  H01L29/45

Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.

公开(公告)号：US20230343699A1

公开(公告)日：2023-10-26

申请号：US17890194

申请日：2022-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsuan LU ,  Lin-Yu HUANG ,  Li-Zhen YU ,  Sheng-Tsung WANG ,  Chung-Liang CHENG ,  Huan-Chieh SU ,  Chih-Hao WANG

IPC: H01L23/522 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/41775 ,  H01L29/41733 ,  H01L23/5283

Abstract: A device includes a substrate, a vertical stack of nanostructure channels over the substrate, a gate structure wrapping around the nanostructure channels, and a source/drain region on the substrate. The device further includes a source/drain contact in contact with the source/drain region. The source/drain contact includes a core layer of a first material. A source/drain via is over and in contact with the source/drain contact. The source/drain via is the first material. A gate via is over and in electrical connection with the gate structure. The gate via is the first material.