公开(公告)号：US20190165176A1

公开(公告)日：2019-05-30

申请号：US15821994

申请日：2017-11-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun WANG ,  Kuo-Yi CHAO ,  Rueijer LIN ,  Chen-Yuan KAO ,  Mei-Yun WANG

IPC: H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure includes a gate electrode layer formed over the gate dielectric later and a gate contact structure formed over the gate electrode layer. The gate contact structure includes a first conductive layer formed over the gate electrode layer, a barrier layer formed over the first conductive layer and a second conductive layer over the barrier layer. The second conductive layer is electrically connected to the gate electrode layer by the first conductive layer.

公开(公告)号：US20200105519A1

公开(公告)日：2020-04-02

申请号：US16146529

申请日：2018-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ting LIN ,  Chen-Yuan KAO ,  Rueijer LIN ,  Yu-Sheng WANG ,  I-Li CHEN ,  Hong-Ming WU

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/417 ,  H01L21/285 ,  H01L21/768

Abstract: The present disclosure describes a method that includes forming a dielectric layer over a contact region on a substrate; etching the dielectric layer to form a contact opening to expose the contact region; and pre-cleaning the exposed contact region to remove a residual material formed by the etching. During the pre-cleaning, the first contact region is exposed to an inductively coupled radio frequency (RF) plasma. Also, during the pre-cleaning, a direct current power supply unit (DC PSU) provides a bias voltage to the substrate and a magnetic field is applied to the inductively coupled RF plasma to collimate ions.

公开(公告)号：US20200058794A1

公开(公告)日：2020-02-20

申请号：US16663085

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun WANG ,  Kuo-Yi CHAO ,  Rueijer LIN ,  Chen-Yuan KAO ,  Mei-Yun WANG

IPC: H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768 ,  H01L29/45 ,  H01L29/417

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure over a substrate and forming a gate dielectric layer over the fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer and forming a source/drain (S/D) structure adjacent to the gate electrode layer. In addition, the method includes forming an S/D contact structure over the S/D structure. The method also includes forming a first conductive layer in direct with the gate electrode layer. A bottom surface of the first conductive layer is lower than a top surface of the gate dielectric layer. The method further includes forming a second conductive layer over the first conductive layer. The gate electrode layer is electrically connected to the second conductive layer by the first conductive layer.

公开(公告)号：US20170200800A1

公开(公告)日：2017-07-13

申请号：US14990009

申请日：2016-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Ping LIU ,  Hung-Chang HSU ,  Hung-Wen SU ,  Ming-Hsing TSAI ,  Rueijer LIN ,  Sheng-Hsuan LIN ,  Ya-Lien LEE ,  Yen-Shou KAO

IPC: H01L29/45 ,  H01L21/311 ,  H01L29/51 ,  H01L21/768

CPC classification number: H01L29/456 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76832 ,  H01L21/76846 ,  H01L21/76856 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a substrate. The method includes removing a first portion of the dielectric layer to form a first hole in the dielectric layer. A second portion of the dielectric layer is under the first hole. The method includes forming a first protection layer over the gate stack and the spacer layer. The method includes forming a second protection layer over the first protection layer. The second protection layer includes a metal compound material, and the first protection layer and the second protection layer includes a same metal element. The method includes removing the second portion of the dielectric layer to form a through hole. The method includes forming a conductive contact structure in the through hole.

公开(公告)号：US20170200612A1

公开(公告)日：2017-07-13

申请号：US15455893

申请日：2017-03-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Rueijer LIN ,  Chen-Yuan KAO ,  Chun-Chieh LIN ,  Huang-Yi HUANG

IPC: H01L21/288 ,  H01L21/285 ,  H01L23/532 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L21/2885 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate. The dielectric layer has a first recess. The method includes forming a first conductive material layer over an inner wall and a bottom of the first recess. The first conductive material layer is partially filled in the first recess. The method includes performing a reflow process to convert the first conductive material layer into a first conductive layer. The first conductive layer has a second recess in the first recess. The method includes performing an electroplating process or an electroless plating process to form a second conductive layer over the first conductive layer so as to fill the second recess.

公开(公告)号：US20160365343A1

公开(公告)日：2016-12-15

申请号：US14739379

申请日：2015-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Yu-Hung LIN ,  Hon-Lin HUANG ,  Rueijer LIN ,  Shih-Chi LIN ,  Sheng-Hsuan LIN

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/31144 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/665 ,  H01L29/6653

Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a gate structure over a substrate and forming a spacer on a sidewall of the gate structure. The method for manufacturing a semiconductor structure further includes forming a hard mask structure on a top surface of the gate structure and on an upper portion of the spacer but not on a bottom portion of the spacer.

Abstract translation: 提供半导体结构及其形成方法。 制造半导体结构的方法包括在衬底上形成栅极结构，并在栅极结构的侧壁上形成间隔物。 制造半导体结构的方法还包括在栅极结构的顶表面上和在间隔物的上部而不是在间隔物的底部上形成硬掩模结构。

公开(公告)号：US20160099216A1

公开(公告)日：2016-04-07

申请号：US14504805

申请日：2014-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Rueijer LIN ,  Chen-Yuan KAO ,  Chun-Chieh LIN ,  Huang-Yi HUANG

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/288 ,  H01L21/285 ,  H01L23/522 ,  H01L27/088

CPC classification number: H01L21/2885 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a dielectric layer positioned on the semiconductor substrate. The dielectric layer has a first recess. The semiconductor device structure includes a conductive structure filling the first recess. The conductive structure includes a first conductive layer and a second conductive layer. The first conductive layer is positioned over an inner wall and a bottom of the first recess. The first conductive layer has a second recess in the first recess. The second conductive layer fills the second recess. The first conductive layer and the second conductive layer include cobalt. The second conductive layer further includes at least one of sulfur, chlorine, boron, phosphorus, or nitrogen.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括半导体衬底。 半导体器件结构包括位于半导体衬底上的电介质层。 电介质层具有第一凹部。 半导体器件结构包括填充第一凹槽的导电结构。 导电结构包括第一导电层和第二导电层。 第一导电层位于第一凹部的内壁和底部之上。 第一导电层在第一凹部中具有第二凹部。 第二导电层填充第二凹槽。 第一导电层和第二导电层包括钴。 第二导电层还包括硫，氯，硼，磷或氮中的至少一种。