公开(公告)号：US20160365343A1

公开(公告)日：2016-12-15

申请号：US14739379

申请日：2015-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Yu-Hung LIN ,  Hon-Lin HUANG ,  Rueijer LIN ,  Shih-Chi LIN ,  Sheng-Hsuan LIN

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/31144 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/665 ,  H01L29/6653

Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a gate structure over a substrate and forming a spacer on a sidewall of the gate structure. The method for manufacturing a semiconductor structure further includes forming a hard mask structure on a top surface of the gate structure and on an upper portion of the spacer but not on a bottom portion of the spacer.

Abstract translation: 提供半导体结构及其形成方法。 制造半导体结构的方法包括在衬底上形成栅极结构，并在栅极结构的侧壁上形成间隔物。 制造半导体结构的方法还包括在栅极结构的顶表面上和在间隔物的上部而不是在间隔物的底部上形成硬掩模结构。

公开(公告)号：US20210280462A1

公开(公告)日：2021-09-09

申请号：US17216444

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Pei CHOU ,  Ken-Yu CHANG ,  Sheng-Hsuan LIN ,  Yueh-Ching PAI ,  Yu-Ting LIN

IPC: H01L21/768 ,  H01L21/285

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.

公开(公告)号：US20190148223A1

公开(公告)日：2019-05-16

申请号：US15967056

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Pei CHOU ,  Ken-Yu CHANG ,  Sheng-Hsuan LIN ,  Yueh-Ching PAI ,  Yu-Ting LIN

IPC: H01L21/768 ,  H01L21/285

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.

公开(公告)号：US20170200800A1

公开(公告)日：2017-07-13

申请号：US14990009

申请日：2016-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Ping LIU ,  Hung-Chang HSU ,  Hung-Wen SU ,  Ming-Hsing TSAI ,  Rueijer LIN ,  Sheng-Hsuan LIN ,  Ya-Lien LEE ,  Yen-Shou KAO

IPC: H01L29/45 ,  H01L21/311 ,  H01L29/51 ,  H01L21/768

CPC classification number: H01L29/456 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76832 ,  H01L21/76846 ,  H01L21/76856 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a substrate. The method includes removing a first portion of the dielectric layer to form a first hole in the dielectric layer. A second portion of the dielectric layer is under the first hole. The method includes forming a first protection layer over the gate stack and the spacer layer. The method includes forming a second protection layer over the first protection layer. The second protection layer includes a metal compound material, and the first protection layer and the second protection layer includes a same metal element. The method includes removing the second portion of the dielectric layer to form a through hole. The method includes forming a conductive contact structure in the through hole.

公开(公告)号：US20250066899A1

公开(公告)日：2025-02-27

申请号：US18454702

申请日：2023-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yen LIAO ,  I. LEE ,  Shu-Lan CHANG ,  Sheng-Hsuan LIN ,  Feng-Yu CHANG ,  Wei-Jung LIN ,  Chun-I TSAI ,  Chih-Chien CHI ,  Ming-Hsing TSAI ,  Pei Shan CHANG ,  Chih-Wei CHANG

IPC: C23C14/04 ,  C23C14/34 ,  C23C14/50 ,  C23C14/54 ,  C23C14/58

Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.

公开(公告)号：US20190273147A1

公开(公告)日：2019-09-05

申请号：US15909838

申请日：2018-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wen CHENG ,  Cheng-Tung LIN ,  Chih-Wei CHANG ,  Hong-Mao LEE ,  Ming-Hsing TSAI ,  Sheng-Hsuan LIN ,  Wei-Jung LIN ,  Yan-Ming TSAI ,  Yu-Shiuan WANG ,  Hung-Hsu CHEN ,  Wei-Yip LOH ,  Ya-Yi CHENG

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L21/326 ,  H01L29/78

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.