公开(公告)号：US20190148556A1

公开(公告)日：2019-05-16

申请号：US16043371

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh WANG ,  Yu-Ting LIN ,  Yueh-Ching PAI ,  Shih-Chieh CHANG ,  Huai-Tei YANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/3065 ,  H01L27/088

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer and a source/drain structure. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The source/drain structure includes a first source/drain epitaxial layer and a second source/drain epitaxial layer. The first source/drain epitaxial layer is in contact with the fin structure. The first source/drain epitaxial layer is connected to a portion of the second source/drain epitaxial layer below a top surface of the fin structure. The lattice constant of the first source/drain epitaxial layer is different from the lattice constant of the second source/drain epitaxial layer.

公开(公告)号：US20200105519A1

公开(公告)日：2020-04-02

申请号：US16146529

申请日：2018-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ting LIN ,  Chen-Yuan KAO ,  Rueijer LIN ,  Yu-Sheng WANG ,  I-Li CHEN ,  Hong-Ming WU

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/417 ,  H01L21/285 ,  H01L21/768

Abstract: The present disclosure describes a method that includes forming a dielectric layer over a contact region on a substrate; etching the dielectric layer to form a contact opening to expose the contact region; and pre-cleaning the exposed contact region to remove a residual material formed by the etching. During the pre-cleaning, the first contact region is exposed to an inductively coupled radio frequency (RF) plasma. Also, during the pre-cleaning, a direct current power supply unit (DC PSU) provides a bias voltage to the substrate and a magnetic field is applied to the inductively coupled RF plasma to collimate ions.

公开(公告)号：US20190164822A1

公开(公告)日：2019-05-30

申请号：US15887819

申请日：2018-02-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Pei CHOU ,  Ken-Yu CHANG ,  Chun-Chieh WANG ,  Yueh-Ching PAI ,  Yu-Ting LIN ,  Yu-Wen CHENG

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L29/78 ,  H01L23/522

CPC classification number: H01L21/76846 ,  C23C16/02 ,  C23C16/0209 ,  C23C16/0227 ,  C23C16/45536 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/823431 ,  H01L23/5226 ,  H01L23/53209 ,  H01L29/41791 ,  H01L29/785 ,  H01L2029/7858

Abstract: The present disclosure relates generally to techniques for forming a continuous adhesion layer for a contact plug. A method includes forming an opening through a dielectric layer to an active area on a substrate. The method includes performing a first plasma treatment along a sidewall of the opening. The method includes performing an atomic layer deposition (ALD) process to form a metal nitride layer along the sidewall of the opening. The ALD process includes a plurality of cycles. Each cycle includes flowing a precursor to form a metal monolayer along the sidewall and performing a second plasma treatment to treat the metal monolayer with nitrogen. The method includes depositing a conductive material on the metal nitride layer in the opening to form a conductive feature.

公开(公告)号：US20210280462A1

公开(公告)日：2021-09-09

申请号：US17216444

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Pei CHOU ,  Ken-Yu CHANG ,  Sheng-Hsuan LIN ,  Yueh-Ching PAI ,  Yu-Ting LIN

IPC: H01L21/768 ,  H01L21/285

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.

公开(公告)号：US20190355585A1

公开(公告)日：2019-11-21

申请号：US15983216

申请日：2018-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei CHANG ,  Kao-Feng LIN ,  Min-Hsiu HUNG ,  Yi-Hsiang CHAO ,  Huang-Yi HUANG ,  Yu-Ting LIN

IPC: H01L21/285 ,  H01L21/28 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

公开(公告)号：US20190164747A1

公开(公告)日：2019-05-30

申请号：US15860354

申请日：2018-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei CHANG ,  Huang-Yi HUANG ,  Chun-chieh WANG ,  Yu-Ting LIN ,  Min-Hsiu HUNG

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

公开(公告)号：US20190148223A1

公开(公告)日：2019-05-16

申请号：US15967056

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Pei CHOU ,  Ken-Yu CHANG ,  Sheng-Hsuan LIN ,  Yueh-Ching PAI ,  Yu-Ting LIN

IPC: H01L21/768 ,  H01L21/285

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.

公开(公告)号：US20230160953A1

公开(公告)日：2023-05-25

申请号：US17832488

申请日：2022-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han WANG ,  Yu-Ting LIN ,  Charlis LIN ,  Coach LIU ,  Wei-Cheng LIU

IPC: G01R31/28 ,  H01L21/768 ,  H01L23/528

CPC classification number: G01R31/2884 ,  H01L21/76898 ,  H01L23/5283 ,  H01L27/088

Abstract: An integrated circuit (IC) chip package and a method of fabricating the same are disclosed. The IC chip package includes a device layer on a first surface of a substrate, a first interconnect structure on the device layer, and a second interconnect structure on the second surface of the substrate. The first interconnect structure includes a fault detection line in a first metal line layer and configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in the device layer, a metal-free region on the fault detection line, and a metal line adjacent to the fault detection line in the first metal line layer. The fault detection line is electrically connected to the device layer.

公开(公告)号：US20240234530A1

公开(公告)日：2024-07-11

申请号：US18330229

申请日：2023-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung TSAI ,  Yu-Ming LIN ,  Kuo-Feng YU ,  Yu-Ting LIN ,  Ming-Te CHEN ,  Yi-Hsiu HUANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: A device includes: a stack of nanostructure channels over a substrate; a gate structure wrapping around the stack; and a source/drain region on the substrate. The source/drain region includes: a first epitaxial layer in direct contact with the channels; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having higher germanium concentration than the first epitaxial layer. The device further includes a bottom isolation structure between the source/drain region and the substrate, the bottom isolation structure being a dielectric layer that is in direct contact with the source/drain region.

公开(公告)号：US20230046911A1

公开(公告)日：2023-02-16

申请号：US17852594

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han WANG ,  Yu-Ting LIN ,  Chia Hong LIN ,  Wei-Cheng LIU

IPC: H01L23/528 ,  G06F30/392

Abstract: The present disclosure describes a structure that includes a substrate with first and second sides, a device layer disposed on the first side of the substrate, having a fault detection area on a back-side surface of the device layer configured to emit a signal that is indicative of a presence or an absence of a defect in the device layer, a first interconnect structure disposed on a front-side of the device layer, and a second interconnect structure disposed on the second side of the substrate, having a metal-free region aligned with the fault detection area and a first metal layer having first and second conductive lines disposed substantially parallel to each other. First and second sidewalls of the first and second conductive lines, respectively, facing each other are substantially aligned with first and second sides of the fault detection area.