公开(公告)号：US20190164747A1

公开(公告)日：2019-05-30

申请号：US15860354

申请日：2018-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei CHANG ,  Huang-Yi HUANG ,  Chun-chieh WANG ,  Yu-Ting LIN ,  Min-Hsiu HUNG

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.