公开(公告)号：US20200381534A1

公开(公告)日：2020-12-03

申请号：US16995253

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Chun-Hsiung TSAI ,  Cheng-Yi PENG ,  Shih-Chieh CHANG ,  Kuo-Feng YU

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: Semiconductor structures are provided. The semiconductor structure includes a fin structure protruding from a substrate and a doped region formed in the fin structure. The semiconductor structure further includes a metal gate structure formed across the fin structure and a gate spacer formed on a sidewall of the metal gate structure. The semiconductor structure further includes a source/drain structure formed over the doped region. In addition, the doped region continuously surrounds the source/drain structure and is in direct contact with the gate spacer.

公开(公告)号：US20170110550A1

公开(公告)日：2017-04-20

申请号：US15062062

申请日：2016-03-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung TSAI ,  Kuo-Feng YU ,  Chien-Tai CHAN ,  Ziwei FANG ,  Kei-Wei CHEN ,  Huai-Tei YANG

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/2254 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/785

Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.

公开(公告)号：US20240234530A1

公开(公告)日：2024-07-11

申请号：US18330229

申请日：2023-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung TSAI ,  Yu-Ming LIN ,  Kuo-Feng YU ,  Yu-Ting LIN ,  Ming-Te CHEN ,  Yi-Hsiu HUANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: A device includes: a stack of nanostructure channels over a substrate; a gate structure wrapping around the stack; and a source/drain region on the substrate. The source/drain region includes: a first epitaxial layer in direct contact with the channels; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having higher germanium concentration than the first epitaxial layer. The device further includes a bottom isolation structure between the source/drain region and the substrate, the bottom isolation structure being a dielectric layer that is in direct contact with the source/drain region.

公开(公告)号：US20170352574A1

公开(公告)日：2017-12-07

申请号：US15171806

申请日：2016-06-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kei-Wei CHEN ,  Chun-Hsiung TSAI ,  Huai-Tei YANG ,  Shiu-Ko JANGJIAN ,  Ying-Lang WANG ,  Ziwei FANG

IPC: H01L21/687 ,  H01L21/3065 ,  H01J37/32 ,  H01L21/67

CPC classification number: H01L21/68764 ,  H01J37/32082 ,  H01J37/32422 ,  H01J37/3244 ,  H01L21/3065

Abstract: An apparatus for treating a wafer is provided. The apparatus includes a platen, a chamber, an etch gas supplier and a tilting mechanism. The chamber has at least one aperture at least partially facing to the platen. The etch gas supplier is fluidly connected to the chamber. The tilting mechanism is coupled with the platen for allowing the platen to have at least one first degree of freedom to tilt relative to the aperture of the chamber.

公开(公告)号：US20160322474A1

公开(公告)日：2016-11-03

申请号：US14866594

申请日：2015-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung TSAI ,  Kei-Wei CHEN

IPC: H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor substrate, n-type source and drain stressors, and a gate stack. The semiconductor substrate has source and drain recesses therein. The n-type source and drain stressors are respectively present in the source and drain recesses. At least one of the n-type source and drain stressors has a hydrogen terminated surface. A gate stack is present on the semiconductor substrate and between the n-type source and drain stressors.

Abstract translation: 半导体结构包括半导体衬底，n型源极和漏极应力源以及栅极堆叠。 半导体衬底在其中具有源极和漏极凹部。 n型源极和漏极应力分别分别存在于源极和漏极的漏极中。 n型源极和漏极应力源中的至少一个具有氢端接表面。 栅极堆叠存在于半导体衬底上以及n型源极和漏极应力源之间。

公开(公告)号：US20200303549A1

公开(公告)日：2020-09-24

申请号：US16898659

申请日：2020-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung TSAI ,  Shahaji B. MORE ,  Cheng-Yi PENG ,  Yu-Ming LIN ,  Kuo-Feng YU ,  Ziwei FANG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/165 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/06

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure extended above a substrate and forming a gate structure formed over a portion of the fin structure. The method also includes forming a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The method further includes doping an outer portion of the S/D structure to form a doped region, and the doped region includes gallium (Ga). The method includes forming a metal silicide layer over the doped region; and forming an S/D contact structure over the metal silicide layer.

公开(公告)号：US20190165143A1

公开(公告)日：2019-05-30

申请号：US15994691

申请日：2018-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Chun-Hsiung TSAI ,  Cheng-Yi PENG ,  Shih-Chieh CHANG ,  Kuo-Feng YU

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762

CPC classification number: H01L29/66492 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7833 ,  H01L29/7851

Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method further includes forming a fin spacer on a sidewall of the fin structure and partially removing the fin spacer. The method further includes recessing the fin structure to form a recess and implanting dopants from the recess to form a doped region. The method further includes diffusing the dopants in the doped region to form an expanded doped region and forming a source/drain structure over the expanded doped region.

公开(公告)号：US20190109213A1

公开(公告)日：2019-04-11

申请号：US16201388

申请日：2018-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung TSAI ,  Kei-Wei CHEN

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08

Abstract: A structure includes a semiconductor substrate, a source epitaxial structure, a drain epitaxial structure, and a gate stack. The source epitaxial structure is in the semiconductor substrate. The source epitaxial structure has a top surface, and the top surface of the source epitaxial structure comprises hydrogen. The drain epitaxial structure is in the semiconductor substrate. The gate stack is over the semiconductor substrate and between the source epitaxial structure and the drain epitaxial structure.

公开(公告)号：US20190363176A1

公开(公告)日：2019-11-28

申请号：US16517204

申请日：2019-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Chun-Hsiung TSAI ,  Cheng-Yi PENG ,  Shih-Chieh CHANG ,  Kuo-Feng YU

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method further includes recessing the fin structure to form a recess and implanting dopants from the recess to form a doped region. The method further includes diffusing the dopants in the doped region to form an expanded doped region and forming a source/drain structure over the expanded doped region.

公开(公告)号：US20190097051A1

公开(公告)日：2019-03-28

申请号：US15893081

申请日：2018-02-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung TSAI ,  Shahaji B. MORE ,  Cheng-Yi PENG ,  Yu-Ming LIN ,  Kuo-Feng YU ,  Ziwei FANG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/165 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/06

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure extended above a substrate and a gate structure formed over a middle portion of the fin structure. The middle portion of the fin structure is wrapped by the gate structure. The FinFET device structure includes a source/drain (S/D) structure adjacent to the gate structure, and the S/D structure includes a doped region at an outer portion of the S/D structure, and the doped region includes gallium (Ga). The FinFET device structure includes a metal silicide layer formed over the doped region of the S/D structure, and the metal silicide layer is in direct contact with the doped region of the S/D structure.