公开(公告)号：US20230160953A1

公开(公告)日：2023-05-25

申请号：US17832488

申请日：2022-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han WANG ,  Yu-Ting LIN ,  Charlis LIN ,  Coach LIU ,  Wei-Cheng LIU

IPC: G01R31/28 ,  H01L21/768 ,  H01L23/528

CPC classification number: G01R31/2884 ,  H01L21/76898 ,  H01L23/5283 ,  H01L27/088

Abstract: An integrated circuit (IC) chip package and a method of fabricating the same are disclosed. The IC chip package includes a device layer on a first surface of a substrate, a first interconnect structure on the device layer, and a second interconnect structure on the second surface of the substrate. The first interconnect structure includes a fault detection line in a first metal line layer and configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in the device layer, a metal-free region on the fault detection line, and a metal line adjacent to the fault detection line in the first metal line layer. The fault detection line is electrically connected to the device layer.

公开(公告)号：US20230046911A1

公开(公告)日：2023-02-16

申请号：US17852594

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han WANG ,  Yu-Ting LIN ,  Chia Hong LIN ,  Wei-Cheng LIU

IPC: H01L23/528 ,  G06F30/392

Abstract: The present disclosure describes a structure that includes a substrate with first and second sides, a device layer disposed on the first side of the substrate, having a fault detection area on a back-side surface of the device layer configured to emit a signal that is indicative of a presence or an absence of a defect in the device layer, a first interconnect structure disposed on a front-side of the device layer, and a second interconnect structure disposed on the second side of the substrate, having a metal-free region aligned with the fault detection area and a first metal layer having first and second conductive lines disposed substantially parallel to each other. First and second sidewalls of the first and second conductive lines, respectively, facing each other are substantially aligned with first and second sides of the fault detection area.