公开(公告)号：US12148816B2

公开(公告)日：2024-11-19

申请号：US17717799

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H Diaz ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/426 ,  H01L21/441 ,  H01L21/461 ,  H01L21/477 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/088 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/092

Abstract: Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

公开(公告)号：US10964691B2

公开(公告)日：2021-03-30

申请号：US16559951

申请日：2019-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz ,  Ta-Pen Guo

IPC: H01L21/74 ,  H01L27/06 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/683 ,  H01L21/306 ,  H01L21/324 ,  H01L29/08 ,  H01L21/822 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8238

Abstract: A method for manufacturing a monolithic three-dimensional (3D) integrated circuit (IC) with junctionless semiconductor devices (JSDs) is provided. A first interlayer dielectric (ILD) layer is formed over a semiconductor substrate, while also forming first vias and first interconnect wires alternatingly stacked in the first ILD layer. A first doping-type layer and a second doping-type layer are transferred to a top surface of the first ILD layer. The first and second doping-type layers are stacked and are semiconductor materials with opposite doping types. The first and second doping-type layers are patterned to form a first doping-type wire and a second doping-type wire overlying the first doping-type wire. A gate electrode is formed straddling the first and second doping-type wires. The gate electrode and the first and second doping-type wires at least partially define a JSD.

公开(公告)号：US20210043756A1

公开(公告)日：2021-02-11

申请号：US17079853

申请日：2020-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L29/267 ,  H01L29/78 ,  H01L27/088 ,  H01L29/04 ,  H01L21/02 ,  H01L29/10 ,  H01L21/477 ,  H01L21/8234 ,  H01L21/8256 ,  H01L29/786 ,  H01L27/06 ,  H01L21/8258 ,  H01L27/12 ,  H01L29/423 ,  H01L21/426 ,  H01L21/441 ,  H01L21/461 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L29/24

Abstract: Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

公开(公告)号：US10461190B2

公开(公告)日：2019-10-29

申请号：US15893316

申请日：2018-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L21/02 ,  H01L29/165 ,  H01L29/417 ,  H01L29/45

Abstract: Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a heavily-doped contact layer disposed between two adjacent layers. The heavily-doped contact layer may be formed through a solid-phase epitaxial regrowth method. The contact resistance may be tuned by adjusting dopant concentration and contact area configuration of the heavily-doped epitaxial contact layer.

公开(公告)号：US20190121582A1

公开(公告)日：2019-04-25

申请号：US16225907

申请日：2018-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz ,  Ta-Pen Guo

IPC: G06F3/06 ,  H01L29/792 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/06 ,  H01L27/11578 ,  H01L27/11514 ,  H01L27/06 ,  H01L21/02 ,  G11C15/04 ,  G11C14/00 ,  G11C13/02

Abstract: Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.

公开(公告)号：US10002922B1

公开(公告)日：2018-06-19

申请号：US15669064

申请日：2017-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz ,  Mark Van Dal

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/465 ,  H01L29/24 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

Abstract: The present disclosure describes a method which can selectively etch silicon from silicon/silicon-germanium stacks or silicon-germanium from silicon-germanium/germanium stacks to form germanium-rich channel nanowires. For example, a method can include a multilayer stack formed with alternating layers of a silicon-rich material and a germanium-rich material. A first thin chalcogenide layer is concurrently formed on the silicon-rich material, and a second thick chalcogenide layer is formed on the germanium-rich material. The first chalcogenide layer and the second chalcogenide layer are etched until the first chalcogenide layer is removed from the silicon-rich material. The silicon-rich material and the second chalcogenide layer are etched with different etch rates.

公开(公告)号：US09941374B2

公开(公告)日：2018-04-10

申请号：US15362470

申请日：2016-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Carlos H. Diaz ,  Chung-Cheng Wu ,  Chia-Hao Chang ,  Chih-Hao Wang ,  Jean-Pierre Colinge ,  Chun-Hsiung Lin ,  Wai-Yi Lien ,  Ying-Keung Leung

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/45 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L29/78 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L29/45 ,  H01L21/76852 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53271 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

公开(公告)号：US09899398B1

公开(公告)日：2018-02-20

申请号：US15220171

申请日：2016-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC: H01L29/788 ,  H01L27/11551 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/49 ,  H01L29/41 ,  H01L29/423

CPC classification number: H01L27/11551 ,  H01L21/28273 ,  H01L29/0673 ,  H01L29/413 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66825

Abstract: Methods are disclosed herein for fabricating non-volatile memory devices. An exemplary method forms a heterostructure over a substrate. The heterostructure includes at least one semiconductor layer pair having a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer, the second semiconductor layer being different than the first semiconductor layer. A gate structure having a dummy gate is formed over a portion of the heterostructure, such that the gate structure separates a source region and a drain region of the heterostructure and a channel region is defined between the source region and the drain region. During a gate replacement process, a nanocrystal floating gate is formed in the channel region from the second semiconductor layer. In some implementations, during the gate replacement process, a nanowire is also formed in the channel region from the first semiconductor layer.

公开(公告)号：US09875902B2

公开(公告)日：2018-01-23

申请号：US15485340

申请日：2017-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC: H01L21/285 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/45

CPC classification number: H01L21/28518 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/465 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer.

公开(公告)号：US20170077253A1

公开(公告)日：2017-03-16

申请号：US15362470

申请日：2016-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Carlos H. Diaz ,  Chung-Cheng Wu ,  Chia-Hao Chang ,  Chih-Hao Wang ,  Jean-Pierre Colinge ,  Chun-Hsiung Lin ,  Wai-Yi Lien ,  Ying-Keung Leung

IPC: H01L29/45 ,  H01L23/528 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L29/45 ,  H01L21/76852 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53271 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain(S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract translation: 公开了一种半导体器件及其形成方法。 半导体器件包括衬底，第一和第二源极/漏极（S / D）区域，第一和第二S / D区域之间的沟道，与沟道接合的栅极以及连接到第一S / D区域的接触特征 。 接触特征包括第一和第二接触层。 第一接触层具有共形截面轮廓，并且在其至少两侧与第一S / D区域接触。 在实施例中，第一接触层与第一S / D区域的三个或四个侧面直接接触，以增加接触面积。 第一接触层包括半导体 - 金属合金，III-V半导体和锗中的一种。