公开(公告)号：US20240387392A1

公开(公告)日：2024-11-21

申请号：US18786873

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hui-Jung Tsai ,  Hung-Jui Kuo ,  Chung-Shi Liu ,  Han-Ping Pu ,  Ting-Chu Ko

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.

公开(公告)号：US12002799B2

公开(公告)日：2024-06-04

申请号：US17814766

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hung-Yi Kuo ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Tsung-Yuan Yu ,  Ming Hung Tseng

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/32 ,  H01L24/03 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.

公开(公告)号：US11984374B2

公开(公告)日：2024-05-14

申请号：US17650932

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L23/3114 ,  H01L21/568

Abstract: A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.

公开(公告)号：US20230369303A1

公开(公告)日：2023-11-16

申请号：US18357457

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Cheng-Chieh Hsieh ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/40 ,  H01L23/31

CPC classification number: H01L25/16 ,  H01L21/561 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/73 ,  H01L23/4012 ,  H01L23/3107 ,  H01L2924/1434 ,  H01L2023/4087 ,  H01L2224/25171 ,  H01L2224/24147 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/73209 ,  H01L2924/1205 ,  H01L2924/1431

Abstract: A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package.

公开(公告)号：US11798925B2

公开(公告)日：2023-10-24

申请号：US17396993

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Cheng-Chieh Hsieh ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L23/40 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/4012 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L2023/4087 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/2518 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2924/1205 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package.

公开(公告)号：US20230307251A1

公开(公告)日：2023-09-28

申请号：US18324686

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Yu-Hsiang Hu ,  Jo-Lin Lan ,  Sih-Hao Liao ,  Chen-Cheng Kuo ,  Hung-Jui Kuo ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Meng-Wei Chou

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L21/561 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2225/06568

Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.

公开(公告)号：US11749626B2

公开(公告)日：2023-09-05

申请号：US17222249

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kai-Chiang Wu ,  Chung-Shi Liu ,  Shou Zen Chang ,  Chao-Wen Shih

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L21/78 ,  H01L23/552 ,  H01L25/10 ,  H01L25/00 ,  H01P3/00 ,  H01Q1/22 ,  H01Q1/38 ,  H01L23/31 ,  H01Q9/04 ,  H01L21/683 ,  H01Q21/06

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01P3/003 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q9/0457 ,  H01L21/486 ,  H01L2221/68331 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/214 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/3025 ,  H01Q21/065

Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.

公开(公告)号：US20230245939A1

公开(公告)日：2023-08-03

申请号：US18297927

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC: H01L23/31 ,  H01L23/16 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528

CPC classification number: H01L23/3157 ,  H01L23/16 ,  H01L23/5226 ,  H01L21/76843 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/528

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US20230230962A1

公开(公告)日：2023-07-20

申请号：US18190341

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Chung-Shi Liu

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L24/81 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/81007 ,  H01L2224/81801 ,  H01L2224/81948 ,  H01L2224/81947 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2224/13147 ,  H01L24/13 ,  H01L2224/11462 ,  H01L2224/05571 ,  H01L2924/381 ,  H01L2224/13101 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16145 ,  H01L2224/81141 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/81815 ,  H01L2924/14 ,  H01L2224/05558

Abstract: An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.

公开(公告)号：US11625940B2

公开(公告)日：2023-04-11

申请号：US17106644

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Yu-Feng Chen ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Chung-Shi Liu

IPC: G06K9/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  G06V40/13

Abstract: A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip.