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Patent Agency Ranking
公开(公告)号：CN103094138B
公开(公告)日：2015-07-22
申请号：CN201210433490.5
申请日：2012-11-02
Applicant: 国际商业机器公司
Inventor： S·V·源
IPC: H01L21/60 , H01L23/488
CPC classification number: H01L23/488 , H01L23/481 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L2224/13025 , H01L2224/13147 , H01L2224/13562 , H01L2224/1357 , H01L2224/1358 , H01L2224/13649 , H01L2224/13655 , H01L2224/13657 , H01L2224/13666 , H01L2224/13676 , H01L2224/13681 , H01L2224/13684 , H01L2224/16145 , H01L2224/16501 , H01L2224/29147 , H01L2224/29564 , H01L2224/2957 , H01L2224/2958 , H01L2224/29649 , H01L2224/29655 , H01L2224/29657 , H01L2224/29666 , H01L2224/29676 , H01L2224/29681 , H01L2224/29684 , H01L2224/32501 , H01L2224/80075 , H01L2224/80097 , H01L2224/80895 , H01L2224/80896 , H01L2224/81005 , H01L2224/81193 , H01L2224/8183 , H01L2224/81895 , H01L2224/83005 , H01L2224/83193 , H01L2224/8383 , H01L2225/06513 , H01L2225/06541 , H01L2924/12042 , H01L2924/1306 , H01L2924/00014 , H01L2924/013 , H01L2924/00012 , H01L2924/053 , H01L2924/00
Abstract: 本发明公开涉及具有增强的铜对铜接合的三维（3D）集成电路及其形成方法。至少在第一器件晶片的Cu表面上形成至少一个金属粘附层。具有另一Cu表面的第二器件晶片被放置在第一器件晶片的Cu表面顶上且在至少一个金属粘附层上面。第一器件晶片和第二器件晶片然后被接合在一起。接合包含在施加或不施加外部施加的压力的情况下在低于400°C的温度下加热器件晶片。在加热期间，两个Cu表面被接合在一起，并且至少一个金属粘附层从两个Cu表面得到氧原子，并且在Cu表面之间形成至少一个金属氧化物接合层。
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公开(公告)号：CN103094138A
公开(公告)日：2013-05-08
申请号：CN201210433490.5
申请日：2012-11-02
Applicant: 国际商业机器公司
Inventor： S·V·源
IPC: H01L21/60 , H01L23/488
CPC classification number: H01L23/488 , H01L23/481 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L2224/13025 , H01L2224/13147 , H01L2224/13562 , H01L2224/1357 , H01L2224/1358 , H01L2224/13649 , H01L2224/13655 , H01L2224/13657 , H01L2224/13666 , H01L2224/13676 , H01L2224/13681 , H01L2224/13684 , H01L2224/16145 , H01L2224/16501 , H01L2224/29147 , H01L2224/29564 , H01L2224/2957 , H01L2224/2958 , H01L2224/29649 , H01L2224/29655 , H01L2224/29657 , H01L2224/29666 , H01L2224/29676 , H01L2224/29681 , H01L2224/29684 , H01L2224/32501 , H01L2224/80075 , H01L2224/80097 , H01L2224/80895 , H01L2224/80896 , H01L2224/81005 , H01L2224/81193 , H01L2224/8183 , H01L2224/81895 , H01L2224/83005 , H01L2224/83193 , H01L2224/8383 , H01L2225/06513 , H01L2225/06541 , H01L2924/12042 , H01L2924/1306 , H01L2924/00014 , H01L2924/013 , H01L2924/00012 , H01L2924/053 , H01L2924/00
Abstract: 本发明公开涉及具有增强的铜对铜接合的三维（3D）集成电路及其形成方法。至少在第一器件晶片的Cu表面上形成至少一个金属粘附层。具有另一Cu表面的第二器件晶片被放置在第一器件晶片的Cu表面顶上且在至少一个金属粘附层上面。第一器件晶片和第二器件晶片然后被接合在一起。接合包含在施加或不施加外部施加的压力的情况下在低于400°C的温度下加热器件晶片。在加热期间，两个Cu表面被接合在一起，并且至少一个金属粘附层从两个Cu表面得到氧原子，并且在Cu表面之间形成至少一个金属氧化物接合层。
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公开(公告)号：CN107785347A
公开(公告)日：2018-03-09
申请号：CN201710733545.7
申请日：2017-08-24
Applicant: 三星显示有限公司
IPC: H01L23/498
CPC classification number: H01L23/49811 , H01L23/3171 , H01L23/3192 , H01L23/53204 , H01L23/53209 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/81 , H01L2224/0401 , H01L2224/05022 , H01L2224/0508 , H01L2224/05567 , H01L2224/0558 , H01L2224/05644 , H01L2224/05666 , H01L2224/13005 , H01L2224/13007 , H01L2224/1301 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13149 , H01L2224/13155 , H01L2224/13157 , H01L2224/1316 , H01L2224/13164 , H01L2224/13166 , H01L2224/13169 , H01L2224/13176 , H01L2224/13178 , H01L2224/13179 , H01L2224/1318 , H01L2224/13181 , H01L2224/13184 , H01L2224/13562 , H01L2224/1358 , H01L2224/13582 , H01L2224/13583 , H01L2224/13611 , H01L2224/13613 , H01L2224/13616 , H01L2224/1362 , H01L2224/13624 , H01L2224/13639 , H01L2224/13644 , H01L2224/13647 , H01L2224/13649 , H01L2224/13655 , H01L2224/13657 , H01L2224/1366 , H01L2224/13664 , H01L2224/13666 , H01L2224/13669 , H01L2224/13673 , H01L2224/13676 , H01L2224/13678 , H01L2224/13679 , H01L2224/1368 , H01L2224/13681 , H01L2224/13684 , H01L2224/1369 , H01L2224/16238 , H01L2224/2919 , H01L2224/73204 , H01L2224/81191 , H01L2224/81193 , H01L2924/00014 , H01L2924/013 , H01L2924/0665 , H01L23/49816
Abstract: 提供了一种半导体芯片和电子装置。该半导体芯片包括：基底；一个或更多个导电焊盘，设置在基底上；一个或更多个凸起，电连接到一个或更多个导电焊盘，其中，一个或更多个凸起包括：金属芯；聚合物层，设置在金属芯的表面的上方；导电涂层，设置在聚合物层的表面的上方并且电连接到一个或更多个导电焊盘。
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公开(公告)号：CN103426849B
公开(公告)日：2016-12-28
申请号：CN201310003803.8
申请日：2013-01-06
Applicant: 台湾积体电路制造股份有限公司
IPC: H01L23/488 , H01L21/60
CPC classification number: H01L23/48 , H01L23/3185 , H01L23/3192 , H01L23/488 , H01L23/52 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/05582 , H01L2224/05583 , H01L2224/05611 , H01L2224/05618 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05676 , H01L2224/05681 , H01L2224/1134 , H01L2224/1146 , H01L2224/11466 , H01L2224/11823 , H01L2224/11825 , H01L2224/1184 , H01L2224/13005 , H01L2224/13019 , H01L2224/13147 , H01L2224/13562 , H01L2224/13582 , H01L2224/13611 , H01L2224/13618 , H01L2224/13639 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2224/13669 , H01L2224/13673 , H01L2224/13676 , H01L2224/29011 , H01L2224/29035 , H01L2224/2919 , H01L2224/73103 , H01L2224/73203 , H01L2224/81193 , H01L2224/81205 , H01L2224/8183 , H01L2224/81895 , H01L2224/83191 , H01L2224/83193 , H01L2224/94 , H01L2924/00014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/014 , H01L2924/01029 , H01L2924/206 , H01L2224/81 , H01L2924/0665 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
Abstract: 一种三维(3D)芯片堆叠件，包括与第二芯片接合的第一芯片。第一芯片包括位于第一衬底上面的第一凸块结构，而第二芯片包括位于第二衬底上面的第二凸块结构。第一凸块结构与第二凸块结构连接，而接合区域在第一凸块结构和第二凸块结构之间形成。该接合区域是包括贵金属的无焊料区域。本发明提供三维芯片堆叠件的形成方法。
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公开(公告)号：CN103426849A
公开(公告)日：2013-12-04
申请号：CN201310003803.8
申请日：2013-01-06
Applicant: 台湾积体电路制造股份有限公司
IPC: H01L23/488 , H01L21/60
CPC classification number: H01L23/48 , H01L23/3185 , H01L23/3192 , H01L23/488 , H01L23/52 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/05582 , H01L2224/05583 , H01L2224/05611 , H01L2224/05618 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05676 , H01L2224/05681 , H01L2224/1134 , H01L2224/1146 , H01L2224/11466 , H01L2224/11823 , H01L2224/11825 , H01L2224/1184 , H01L2224/13005 , H01L2224/13019 , H01L2224/13147 , H01L2224/13562 , H01L2224/13582 , H01L2224/13611 , H01L2224/13618 , H01L2224/13639 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2224/13669 , H01L2224/13673 , H01L2224/13676 , H01L2224/29011 , H01L2224/29035 , H01L2224/2919 , H01L2224/73103 , H01L2224/73203 , H01L2224/81193 , H01L2224/81205 , H01L2224/8183 , H01L2224/81895 , H01L2224/83191 , H01L2224/83193 , H01L2224/94 , H01L2924/00014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/014 , H01L2924/01029 , H01L2924/206 , H01L2224/81 , H01L2924/0665 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
Abstract: 一种三维(3D)芯片堆叠件，包括与第二芯片接合的第一芯片。第一芯片包括位于第一衬底上面的第一凸块结构，而第二芯片包括位于第二衬底上面的第二凸块结构。第一凸块结构与第二凸块结构连接，而接合区域在第一凸块结构和第二凸块结构之间形成。该接合区域是包括贵金属的无焊料区域。本发明提供三维芯片堆叠件的形成方法。
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