公开(公告)号：US12084790B2

公开(公告)日：2024-09-10

申请号：US18337493

申请日：2023-06-20

申请人： AXT, Inc.

发明人： Rajaram Shetty ,  Weiguo Liu ,  Morris Young

IPC分类号： C30B29/42 ,  C30B11/00 ,  H01L29/20 ,  H01L29/32 ,  H01L29/36 ,  H01L29/30 ,  H01S5/30

CPC分类号： C30B29/42 ,  C30B11/002 ,  C30B11/006 ,  H01L29/20 ,  H01L29/32 ,  H01L29/36 ,  H01L29/30 ,  H01S5/3013

摘要： Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm−2, and a resistivity of 1×107 Ω-cm or more. The wafer may have an optical absorption of less than 5 cm−1 less than 4 cm−1 or less than 3 cm−1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 μm or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm−3 or less.

公开(公告)号：US11821105B2

公开(公告)日：2023-11-21

申请号：US17385912

申请日：2021-07-27

申请人： GlobalWafers Co., Ltd.

发明人： Ching-Shan Lin

IPC分类号： C30B23/02 ,  C30B29/36 ,  C30B23/06 ,  C01B32/956 ,  H01L29/30

CPC分类号： C30B23/025 ,  C30B23/066 ,  C30B29/36 ,  C01B32/956 ,  H01L29/30

摘要： The disclosure provides a silicon carbide seed crystal and a method of manufacturing a silicon carbide ingot. The silicon carbide seed crystal has a silicon surface and a carbon surface opposite to the silicon surface. A difference D between a basal plane dislocation density BPD1 of the silicon surface and a basal plane dislocation density BPD2 of the carbon surface satisfies the following formula (1), a local thickness variation (LTV) of the silicon carbide seed crystal is 2.5 μm or less, and a stacking fault (SF) density of the silicon carbide seed crystal is 10 EA/cm2 or less:

D=(BPD1−BPD2)/BPD1≤25%  (1).

公开(公告)号：US11680340B2

公开(公告)日：2023-06-20

申请号：US16711019

申请日：2019-12-11

申请人： AXT, Inc.

发明人： Rajaram Shetty ,  Weiguo Liu ,  Morris Young

IPC分类号： C30B29/42 ,  C30B11/00 ,  H01L29/36 ,  H01L29/20 ,  H01L29/32 ,  H01L29/30 ,  H01S5/30

CPC分类号： C30B29/42 ,  C30B11/002 ,  C30B11/006 ,  H01L29/20 ,  H01L29/32 ,  H01L29/36 ,  H01L29/30 ,  H01S5/3013

摘要： Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm−2, and a resistivity of 1×107 Ω-cm or more. The wafer may have an optical absorption of less than 5 cm−1 less than 4 cm−1 or less than 3 cm−1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 μm or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm−3 or less.

公开(公告)号：US11094549B2

公开(公告)日：2021-08-17

申请号：US16641538

申请日：2018-06-29

申请人： BEIJING TONGMEI XTAL TECHNOLOGY CO., LTD.

发明人： Liugang Wang ,  Haimiao Li ,  Sung-Nee George Chu

IPC分类号： H01L21/306 ,  B24B37/08 ,  C30B29/40 ,  H01L29/30

摘要： A {100} indium phosphide (InP) wafer with pits distributed on the back side thereof, a method and an etching solution for manufacturing thereof are provided, wherein the pits on the back side have an elongated shape with a maximum dimension of the long axis of 65 μm, and the pits have a maximum depth of 6.0 μm. The {100} indium phosphide (InP) wafer has controllable pits distribution on the back side, thus provide a controllable emissivity of the wafer back side surface for better control of wafer back side heating during the epitaxial growth.

公开(公告)号：US10541181B2

公开(公告)日：2020-01-21

申请号：US16401417

申请日：2019-05-02

申请人： SK SILTRON CO., LTD.

发明人： Jae Hyeong Lee

IPC分类号： H01L29/30 ,  H01L21/66 ,  H01L29/32 ,  H01L21/324

摘要： A wafer defect analysis method according to one embodiment comprises the steps of: thermally treating a wafer at different temperatures; measuring an oxygen precipitate index of the thermally treated wafer; determining a characteristic temperature at which the oxygen precipitate index is maximized; and discriminating a type of defect region of the wafer depending on the determined characteristic temperature.

公开(公告)号：US09978582B2

公开(公告)日：2018-05-22

申请号：US15379759

申请日：2016-12-15

申请人： Ostendo Technologies, Inc.

发明人： Gregory Batinica ,  Kameshwar Yadavalli ,  Qian Fan ,  Benjamin A. Haskell ,  Hussein S. El-Ghoroury

IPC分类号： H01L21/302 ,  H01L21/02 ,  H01L21/66 ,  H01L23/31 ,  H01L23/00 ,  H01L29/20 ,  H01L29/30

CPC分类号： H01L21/02035 ,  H01L21/02002 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02172 ,  H01L21/02274 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3171 ,  H01L23/562 ,  H01L24/94 ,  H01L29/2003 ,  H01L29/30 ,  H01L2224/94 ,  H01L2924/3511

摘要： A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO2 having a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.

公开(公告)号：US09831115B2

公开(公告)日：2017-11-28

申请号：US15435428

申请日：2017-02-17

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Andrew M. Jones ,  Srikanth Kommu ,  Jeffrey L. Libbert

IPC分类号： H01L21/762 ,  H01L21/324 ,  H01L29/04 ,  H01L29/40 ,  H01L29/30 ,  H01L21/28 ,  H01L21/18 ,  H01L21/265

CPC分类号： H01L21/76251 ,  H01L21/187 ,  H01L21/26506 ,  H01L21/28282 ,  H01L21/76254 ,  H01L29/045 ,  H01L29/30 ,  H01L29/408

摘要： A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

公开(公告)号：US09786742B2

公开(公告)日：2017-10-10

申请号：US15067438

申请日：2016-03-11

申请人： Kabushiki Kaisha Toshiba

发明人： Takuma Suzuki ,  Hiroshi Kono

IPC分类号： H01L29/16 ,  H01L29/08 ,  H01L29/10 ,  H01L29/30 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/1608 ,  H01L21/047 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/30 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802

摘要： A semiconductor device according to an embodiment includes a SiC layer having a first plane and a second plane, a gate insulating film provided on the first plane, a gate electrode provided on the gate insulating film, a first SiC region of a first conductivity type provided in the SiC layer, a second SiC region of a second conductivity type provided in the first SiC region, a third SiC region of the first conductivity type provided in the second SiC region, and a fourth SiC region of the first conductivity type provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC regions, and the fourth SiC region provided between the first SiC region and the third SiC region.

公开(公告)号：US20170263501A1

公开(公告)日：2017-09-14

申请号：US15427380

申请日：2017-02-08

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： BUNZI MIZUNO ,  SHOGO OKITA ,  NORIYUKI MATSUBARA ,  ATSUSHI HARIKAI ,  MITSURU HIROSHIMA

IPC分类号： H01L21/78 ,  H01L29/30 ,  H01L23/31 ,  H01L21/56 ,  H01L21/311

CPC分类号： H01L21/78 ,  H01L21/311 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3171 ,  H01L23/3185 ,  H01L29/30

摘要： A method for manufacturing an element chip includes a laser dicing step of dividing the substrate to a plurality of element chips including the element region by irradiating the dividing region of the substrate with laser light, in a state of supported by a supporting member and forming a damaged region on an end surface of the element chip. Furthermore, the method for manufacturing an element chip includes a protection film stacking step of stacking a protection film on the first main surface and the end surface of the element chip, after the laser dicing step and a protection film etching step of removing the protection film stacked on the first main surface through etching the protection film anisotropically by exposing the element chip to plasma, after the protection film stacking, step and remaining the protection film for covering the damaged region.

公开(公告)号：US20170256633A1

公开(公告)日：2017-09-07

申请号：US15431488

申请日：2017-02-13

申请人： UNIST (Ulsan National Institute of Science and Technology)

发明人： Ki Suk LEE ,  Dae Han JEONG ,  Hee Sung HAN ,  Nam Kyu KIM

IPC分类号： H01L29/66 ,  H01L29/82 ,  H01L29/30

CPC分类号： H01L29/66984 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L29/30 ,  H01L29/82 ,  H01L43/00

摘要： The present disclosure provides a skyrmion diode using skyrmions as information carriers. The skyrmion diode includes a magnetic body and a conductive body. The magnetic body has a skyrmion which is used as information carrier. The conductive body is disposed on or under the magnetic body. The conductive body includes a Dzyaloshinskii-Moriya interaction (DMI) region and a defect region. The DMI region is provided to induce DMI in a region of the magnetic body corresponding to the DMI region by the spin-orbit coupling of the conductive body and magnetic moments of the magnetic body. The defect region is provided to prevent the DMI from being induced in a region of the magnetic body corresponding to the defect region.