公开(公告)号：US10475695B2

公开(公告)日：2019-11-12

申请号：US15899636

申请日：2018-02-20

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Jeffrey L. Libbert

IPC分类号： H01L21/762 ,  H01L21/304 ,  H01L21/02 ,  H01L21/761 ,  H01L29/06 ,  H01L21/322 ,  H01L21/265

摘要： A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

公开(公告)号：US20180233420A1

公开(公告)日：2018-08-16

申请号：US15893055

申请日：2018-02-09

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Rapoport ,  Srikanth Kommu ,  Igor Peidous ,  Gang Wang ,  Jeffrey L. Libbert

IPC分类号： H01L21/66 ,  H01L23/66

CPC分类号： H01L22/14 ,  G01R31/2648 ,  H01L22/20 ,  H01L23/66 ,  H01L27/12

摘要： Methods for assessing the quality of a semiconductor structure having a charge trapping layer to, for example, determine if the structure is suitable for use as a radiofrequency device are disclosed. Embodiments of the assessing method may involve measuring an electrostatic parameter at an initial state and at an excited state in which charge carriers are generated.

公开(公告)号：US09768056B2

公开(公告)日：2017-09-19

申请号：US14524693

申请日：2014-10-27

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Illaria Katia Marianna Pellicano

IPC分类号： H01L21/02 ,  H01L21/762

CPC分类号： H01L21/76251 ,  H01L21/02238 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262

摘要： A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.

公开(公告)号：US10269617B2

公开(公告)日：2019-04-23

申请号：US15623519

申请日：2017-06-15

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Jeffrey L. Libbert

IPC分类号： H01L21/762 ,  H01L21/304 ,  H01L21/02 ,  H01L21/761 ,  H01L29/06 ,  H01L21/322 ,  H01L21/265

摘要： A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

公开(公告)号：US20170365506A1

公开(公告)日：2017-12-21

申请号：US15675001

申请日：2017-08-11

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Illaria Katia Marianna Pellicano

IPC分类号： H01L21/762 ,  H01L21/02

CPC分类号： H01L21/76251 ,  H01L21/02238 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262

摘要： A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.

公开(公告)号：US20170243781A1

公开(公告)日：2017-08-24

申请号：US15435428

申请日：2017-02-17

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Andrew M. Jones ,  Srikanth Kommu ,  Jeffrey L. Libbert

IPC分类号： H01L21/762 ,  H01L29/40 ,  H01L21/265 ,  H01L21/28 ,  H01L21/18 ,  H01L29/04 ,  H01L29/30

CPC分类号： H01L21/76251 ,  H01L21/187 ,  H01L21/26506 ,  H01L21/28282 ,  H01L21/76254 ,  H01L29/045 ,  H01L29/30 ,  H01L29/408

摘要： A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

公开(公告)号：US20150115480A1

公开(公告)日：2015-04-30

申请号：US14524693

申请日：2014-10-27

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Illaria Katia Marianna Pellicano

IPC分类号： H01L21/762 ,  H01L29/16 ,  H01L21/02

CPC分类号： H01L21/76251 ,  H01L21/02238 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262

摘要： A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.

摘要翻译： 提供了在制造绝缘体上硅器件时制备单晶半导体处理晶片的方法。 该方法包括在高电阻率单晶半导体处理晶片的电介质层上形成多层钝化的半导体层。 该方法还包括在钝化半导体层的多层上形成半导体氧化物层。 钝化半导体层的多层包括适合用作绝缘体半导体结构中的高电阻率衬底和掩埋氧化物层之间的电荷俘获层的材料。

公开(公告)号：US10381260B2

公开(公告)日：2019-08-13

申请号：US15526798

申请日：2015-11-13

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Jeffrey L. Libbert ,  Srikanth Kommu ,  Andrew M. Jones ,  Samuel Christopher Pratt ,  Horacio Josue Mendez ,  Leslie George Stanton ,  Michelle Rene Dickinson

IPC分类号： H01L21/762 ,  H01L21/02

摘要： A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.

公开(公告)号：US20180277421A1

公开(公告)日：2018-09-27

申请号：US15984586

申请日：2018-05-21

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Jeffrey L. Libbert ,  Srikanth Kommu ,  Andrew Marquis Jones ,  Samuel Christopher Pratt ,  Horacio Josue Mendez ,  Leslie George Stanton ,  Michelle Rene Dickinson

IPC分类号： H01L21/762 ,  H01L21/02

CPC分类号： H01L21/76251 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/76254

摘要： A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.

公开(公告)号：US09831115B2

公开(公告)日：2017-11-28

申请号：US15435428

申请日：2017-02-17

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Andrew M. Jones ,  Srikanth Kommu ,  Jeffrey L. Libbert

IPC分类号： H01L21/762 ,  H01L21/324 ,  H01L29/04 ,  H01L29/40 ,  H01L29/30 ,  H01L21/28 ,  H01L21/18 ,  H01L21/265

CPC分类号： H01L21/76251 ,  H01L21/187 ,  H01L21/26506 ,  H01L21/28282 ,  H01L21/76254 ,  H01L29/045 ,  H01L29/30 ,  H01L29/408

摘要： A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).