公开(公告)号：US20170263526A1

公开(公告)日：2017-09-14

申请号：US15427548

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： BUNZI MIZUNO ,  MITSURU HIROSHIMA ,  SHOGO OKITA ,  NORIYUKI MATSUBARA ,  ATSUSHI HARIKAI

IPC: H01L23/31 ,  H01L21/78 ,  H01L21/428 ,  H01L21/56 ,  H01L21/311 ,  H01L23/544

CPC classification number: H01L23/3192 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/428 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2223/5446

Abstract: A method for manufacturing an element chip includes a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region through etching the protection film anisotropically by exposing the substrate to first plasma and remaining the protection film for covering an end surface of the element region. Furthermore, the method for manufacturing an element chip includes an isotropic etching step of etching the dividing region isotropically by exposing the substrate to second plasma and a plasma dicing step of dividing the substrate to a plurality of element chips including the element region by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.

公开(公告)号：US20170229385A1

公开(公告)日：2017-08-10

申请号：US15408770

申请日：2017-01-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI HARIKAI ,  SHOGO OKITA ,  NORIYUKI MATSUBARA

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3171 ,  H01L24/09 ,  H01L24/89 ,  H01L2224/80801 ,  H01L2924/15323

Abstract: To provide a method of manufacturing an element chip in which creep-up of a conductive material can be suppressed in a mounting step. In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by an insulating film, the substrate is divided into the element chips by exposing the substrate to a first plasma, the element chips having a first surface, a second surface, and a side surface are held spaced from each other on a carrier, and the side surface and the insulating film are in a state of being exposed.

公开(公告)号：US20170098591A1

公开(公告)日：2017-04-06

申请号：US15264921

申请日：2016-09-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI HARIKAI ,  SHOGO OKITA ,  NORIYUKI MATSUBARA ,  MITSURU HIROSHIMA ,  MITSUHIRO OKUNE

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L23/3185 ,  H01L21/0212 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/293 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: In a plasma processing step in a method of manufacturing an element chip in which a plurality of element chips are manufactured by dividing a substrate, which has a plurality of element regions, the substrate is divided into element chips by exposing the substrate to first plasma. In a protection film forming step of forming a protection film covering a side surface and a second surface by exposing the element chips to second plasma of which raw material gas is mixed gas of carbon fluoride and helium, protection film forming conditions are set such that a thickness of a second protection film of the second surface is greater than a thickness of a first protection film of the side surface.

公开(公告)号：US20180012802A1

公开(公告)日：2018-01-11

申请号：US15622250

申请日：2017-06-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SHOGO OKITA ,  MITSURU HIROSHIMA ,  ATSUSHI HARIKAI ,  NORIYUKI MATSUBARA ,  AKIHIRO ITOU

IPC: H01L21/78 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/78 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31138

Abstract: A semiconductor chip manufacturing method includes preparing a semiconductor wafer including a front surface on which a bump is exposed, a rear surface located at a side opposite to the front surface, a plurality of element regions in each of which the bump is formed, and a dividing region defining each of the element regions, forming a mask which covers the bump and has an opening exposing the dividing region on the surface of the semiconductor wafer by spraying liquid which contains raw material of the mask along the bump by a spray coating method, and singulating the semiconductor wafer by exposing the surface of the semiconductor wafer to first plasma and etching the dividing region, which is exposed to the opening, until the rear surface is reached in a state where the bump is covered by the mask.

公开(公告)号：US20170256412A1

公开(公告)日：2017-09-07

申请号：US15426192

申请日：2017-02-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SHOGO OKITA ,  ATSUSHI HARIKAI

IPC: H01L21/3065 ,  H01L21/677 ,  H01L21/308

CPC classification number: H01L21/3065 ,  H01L21/30655 ,  H01L21/308 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/677 ,  H01L21/6831 ,  H01L21/68742 ,  H01L21/68785 ,  H01L21/78

Abstract: The yield of a product is improved when a substrate held by a conveyance carrier is subjected to a plasma treatment. A plasma treatment method of the substrate held by the conveyance carrier includes preparing the conveyance carrier which includes a holding sheet and a frame disposed on the outer peripheral portion of the holding sheet; bonding the substrate to the holding sheet so that the substrate is held by the conveyance carrier; and increasing tensile strength of the holding sheet. The plasma treatment method further includes placing the conveyance carrier on the stage after the bonding of the substrate and bringing the substrate into contact with the stage through the holding sheet; and performing a plasma treatment on the substrate after the placing of the conveyance carrier.

公开(公告)号：US20170229365A1

公开(公告)日：2017-08-10

申请号：US15408703

申请日：2017-01-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI HARIKAI ,  SHOGO OKITA ,  NORIYUKI MATSUBARA ,  MITSURU HIROSHIMA ,  MITSUHIRO OKUNE

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/3065 ,  H01L21/02 ,  H01L23/544 ,  H01L21/78

Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into element chips 10 by exposing the substrate to a first plasma. Therefore, element chips having a first surface, a second surface, and a side surface connecting the first surface and the second surface are held spaced from each other on a carrier. A protection film covering the element chip is formed only on the side surface and it is possible to suppress creep-up of a conductive material to the side surface in the mounting step by exposing the element chips to second plasma in which a mixed gas of fluorocarbon and helium is used as a raw material gas.

公开(公告)号：US20170069536A1

公开(公告)日：2017-03-09

申请号：US15245139

申请日：2016-08-23

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI HARIKAI ,  NORIYUKI MATSUBARA ,  HIDEO KANOU ,  MITSURU HIROSHIMA ,  SYOUZOU WATANABE ,  TOSHIHIRO WADA

IPC: H01L21/78 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/76826 ,  H01L21/78

Abstract: Provided is a plasma treatment method including: placing a substrate carrier holding a substrate on a stage; adjusting a distance between a cover and the stage to a first distance in which the cover covers a frame without coming into contact with the substrate carrier; performing a plasma treatment on the substrate placed on the stage after the adjusting of the distance; carrying the substrate together with the substrate carrier out from a reaction chamber after the performing of the plasma treatment; and removing an adhered substance adhered to the cover by generating plasma in the inside of the reaction chamber after the carrying of the substrate, in which the distance between the cover and the stage in the removing of the adhered substance is a second distance greater than the first distance.

Abstract translation: 提供了一种等离子体处理方法，包括：将保持衬底的衬底载体放置在平台上; 将盖和台架之间的距离调整到第一距离，其中盖子覆盖框架而不与基板载体接触; 在调整距离后，在放置在舞台上的基板上进行等离子体处理; 在执行等离子体处理之后将基板与基板载体一起从反应室中输出; 以及在承载基板之后，通过在反应室内部产生等离子体，除去附着在盖子上的附着物质，其中盖子和移除粘合物质的台阶之间的距离比第二距离大 第一距离

公开(公告)号：US20170345715A1

公开(公告)日：2017-11-30

申请号：US15594690

申请日：2017-05-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI HARIKAI ,  SHOGO OKITA ,  AKIHIRO ITOU ,  KATSUMI TAKANO ,  MITSURU HIROSHIMA

IPC: H01L21/78 ,  H01L21/683 ,  H01L21/3065 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/3065 ,  H01L21/6836 ,  H01L24/11 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2224/13022

Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface provided with a bump and a second surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of adhering a protection tape having an adhesive layer to the first surface and embedding. The element chip manufacturing method includes a thinning process of grinding the second surface in a state where the protection tape is adhered to the first surface and thinning the substrate, after the bump embedding process, a mask forming process of forming a mask in the second surface and exposes the dividing regions, after the thinning process, a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape.

公开(公告)号：US20170271194A1

公开(公告)日：2017-09-21

申请号：US15427590

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SHOGO OKITA ,  ATSUSHI HARIKAI ,  AKIHIRO ITOU

IPC: H01L21/687 ,  H01L21/67 ,  H01J37/32 ,  H01L21/3065

CPC classification number: H01L21/68785 ,  H01J37/32082 ,  H01J37/32715 ,  H01J37/32724 ,  H01J37/32935 ,  H01J37/3299 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/67248 ,  H01L21/67259 ,  H01L21/67288 ,  H01L21/6831 ,  H01L21/68742

Abstract: A plasma processing method includes a mounting process of mounting a holding sheet holding a substrate in a stage provided in a plasma processing apparatus, and a fixing process of fixing the holding sheet to the stage. The plasma processing method further includes a determining process of determining whether or not a contact state of the holding sheet with the stage is good or bad after the fixing process, and a plasma etching process of etching the substrate by exposing a surface of the substrate to plasma on the stage, in a case in which the contact state is determined to be good in the determining process.

公开(公告)号：US20170263461A1

公开(公告)日：2017-09-14

申请号：US15427198

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： NORIYUKI MATSUBARA ,  ATSUSHI HARIKAI ,  AKIHIRO ITOU

IPC: H01L21/3065 ,  H01L21/78 ,  H01L21/268 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/3065 ,  H01L21/268 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31133 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/6831 ,  H01L21/68742 ,  H01L21/68785 ,  H01L21/78

Abstract: A plasma processing method includes an attaching process of attaching a resin film to a first main surface of a substrate which is provided with the first main surface and a second main surface on an opposite side of the first main surface and a patterning process of forming a mask, which includes an opening exposing a region to be processed of the substrate, by patterning the resin film. The plasma processing method includes a first plasma process of generating first plasma of first gas in a depressurized atmosphere including the first gas, exposing the mask to the first plasma, and reducing a void between the mask and the first main surface. The plasma processing method includes a second plasma process of generating second plasma from second gas in atmosphere including the second gas, exposing the region to be processed exposed from the opening to the second plasma, and etching the region to be processed.