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15 条记录 (耗时 0.018 秒)

    SRAM-based authentication circuit
    1.
    发明授权
    SRAM-based authentication circuit 有权

    公开(公告)号：US11012246B2

    公开(公告)日：2021-05-18

    申请号：US15259948

    申请日：2016-09-08

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Shih-Lien Linus Lu ,  Wei-Min Chan ,  Chien-Chen Lin

    IPC分类号： H04L9/32 ,  G11C7/20 ,  G11C8/12 ,  H04L9/08 ,  G06F12/14 ,  G11C11/417 ,  G11C29/14 ,  G11C16/34 ,  G11C29/44

    摘要： A memory device includes a memory block comprises a plurality of bits, wherein at least a first bit of the plurality of bits presents an initial logic state each time it is powered on; a start-up circuit configured to power on and off the memory block N times, where N is an odd integer greater than 1, and wherein the at least first bit presents an initial state after each respective power cycle of the memory block; and an authentication circuit, coupled to the memory block, and comprising an election engine that is configured to elect an initial state that occurs (N+1)/2 or more times after N power cycles that are performed by the start-up circuit, as a majority initial logic state for the first bit.

    SRAM-based authentication circuit
    2.
    发明授权
    SRAM-based authentication circuit 有权

    公开(公告)号：US10439827B2

    公开(公告)日：2019-10-08

    申请号：US15288382

    申请日：2016-10-07

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chien-Chen Lin ,  Shih-Lien Linus Lu ,  Wei-Min Chan

    IPC分类号： G11C11/419 ,  H04L9/32 ,  G06F12/14 ,  G06F21/44 ,  G06F21/73

    摘要： A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a reduced read margin or a reduced write margin condition to determine a stability of the first bit by detecting whether the first logical state flips to a second logical state, and based on the determined stability of at least the first bit, to generate a physically unclonable function (PUF) signature.

    Memory cell
    7.
    发明授权
    Memory cell 有权

    公开(公告)号：US10964389B2

    公开(公告)日：2021-03-30

    申请号：US16911049

    申请日：2020-06-24

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

    IPC分类号： G11C15/00 ,  G11C15/04 ,  H01L27/02 ,  G11C11/412

    摘要： A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.