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公开(公告)号：US20230318581A1
公开(公告)日：2023-10-05
申请号：US18330492
申请日：2023-06-07
发明人： Chia-Chen KUO , Yangsyu Lin , Yu-Hao Hsu , Cheng Hung Lee , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： H03K3/012
CPC分类号： H03K3/012
摘要： The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.
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公开(公告)号：US10685686B2
公开(公告)日：2020-06-16
申请号：US16582029
申请日：2019-09-25
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC分类号： G11C5/14 , H03K17/687 , H03K17/22
摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
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公开(公告)号：US20150058664A1
公开(公告)日：2015-02-26
申请号：US13972082
申请日：2013-08-21
发明人： Fu-An Wu , Jung-Ping Yang , Chia-En Huang , Cheng Hung Lee
CPC分类号： G06F11/25 , G11C29/00 , G11C29/808 , G11C29/848
摘要： A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation.
摘要翻译： 存储器芯片包括具有多个存储器列的主存储器阵列，与主存储器阵列相关联的冗余存储器列，以及命中逻辑电路，其被配置为通过命中中的多个命中逻辑单元产生多个命中逻辑信号 逻辑电路，用于在存储器列之一中动态替换存储器列之一中的有缺陷的存储器单元，以便在存储器阵列运行时由冗余存储器列进行动态替换。
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公开(公告)号：US20140266436A1
公开(公告)日：2014-09-18
申请号：US13888620
申请日：2013-05-07
发明人： Cheng Hung Lee , Hektor Huang , Chi-Kai Hsieh , Shi-Wei Chang , Hong-Chen Cheng
IPC分类号： H03F3/45
CPC分类号： H03F3/45076 , G11C7/02 , G11C7/065 , G11C7/08 , G11C7/1048
摘要： The present disclosure relates to a differential sense amplifier comprising first and second cross-coupled inverters with first and second complimentary storage nodes. A first current control element changes a current through the first cross-coupled inverter based upon an output of a second cross-coupled inverter, and a second current control element changes a current through the second cross-coupled inverter based upon an output of the first cross-coupled inverter. Other devices and methods are also disclosed.
摘要翻译： 本公开涉及一种差分读出放大器，包括具有第一和第二互补存储节点的第一和第二交叉耦合的反相器。 第一电流控制元件基于第二交叉耦合逆变器的输出改变通过第一交叉耦合逆变器的电流，并且第二电流控制元件基于第一交流耦合逆变器的输出改变通过第二交叉耦合逆变器的电流 交叉耦合逆变器。 还公开了其它装置和方法。
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公开(公告)号：US10972292B2
公开(公告)日：2021-04-06
申请号：US16383383
申请日：2019-04-12
IPC分类号： H04L9/32 , G11C7/06 , G11C11/4091 , H04L9/08
摘要： Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.
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公开(公告)号：US10762934B2
公开(公告)日：2020-09-01
申请号：US16263904
申请日：2019-01-31
发明人： Shang-Chi Wu , Cheng Hung Lee , Chien-Kuo Su , Chiting Cheng , Yu-Hao Hsu , Yangsyu Lin
摘要： The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices. This specialized circuitry, also referred to as a write driver, writes the electronic data onto these data lines for storage in the one or more memory cells during the write mode of operation.
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公开(公告)号：US10510380B2
公开(公告)日：2019-12-17
申请号：US16391986
申请日：2019-04-23
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC分类号： G11C5/14 , H03K17/687 , H03K17/22
摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
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公开(公告)号：US20190252008A1
公开(公告)日：2019-08-15
申请号：US16391986
申请日：2019-04-23
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC分类号： G11C5/14 , H03K17/22 , H03K17/687
摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
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公开(公告)号：US20170272075A1
公开(公告)日：2017-09-21
申请号：US15073948
申请日：2016-03-18
发明人： Chien-Yuan Chen , Cheng Hung Lee , Hung-Jen Liao , Hau-Tai Shieh , Che-Ju Yeh
IPC分类号： H03K19/0185
CPC分类号： H03K19/018521
摘要： A circuit is disclosed. The circuit includes eight MOD transistors and a capacitor, the first MOS transistor having a source coupled to a first predetermined supply voltage (VDDM), a second MOS transistor having a source coupled to a first predetermined supply voltage VDDM, a third MOS transistor having a source coupled to a drain of the first MOS transistor, a fourth MOS transistor having a source coupled to a drain of the second MOS transistor, a fifth MOS transistor having a source coupled to a drain of the third MOS transistor and a gate of the second MOS transistor, and a gate coupled to a gate of the third MOS transistor and an input node, and a drain coupled to ground, a sixth MOS transistor having a source coupled to a drain of the fourth MOS transistor and a gate of the first MOS transistor and an output node.
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公开(公告)号：US09659603B2
公开(公告)日：2017-05-23
申请号：US14980287
申请日：2015-12-28
发明人： Hektor Huang , Yangsyu Lin , Yu-Hao Hsu , Chia-En Huang , Chiting Cheng , Chen-Lin Yang , Jung-Ping Yang , Cheng Hung Lee
摘要： A power management circuit for an electronic device sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits. The power management circuit continues to sequentially provide each of the one or more circuit power management signals in a similar manner until the electronic circuits of the electronic device have been activated and/or deactivated.
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