公开(公告)号：US10685686B2

公开(公告)日：2020-06-16

申请号：US16582029

申请日：2019-09-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fu-An Wu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yu-Hao Hsu

IPC分类号： G11C5/14 ,  H03K17/687 ,  H03K17/22

摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

公开(公告)号：US09007859B2

公开(公告)日：2015-04-14

申请号：US14316857

申请日：2014-06-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Lin Yang ,  Chung-Yi Wu ,  Yu-Hao Hsu

IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/413

CPC分类号： G11C7/12 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

摘要： A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline row has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.

摘要翻译： 公开了一种字线跟踪电路和相应的方法，并且包括具有与之相关联的阻抗特性的跟踪字线，其对存储器件中的一行存储器单元进行建模，其中跟踪字线行具有近端，其接收具有 近端上升脉冲沿和近端下降脉冲沿。 跟踪字线也有一个远端。 跟踪单元组件耦合到接收字线脉冲信号的跟踪字线的远端。 最后，电路包括耦合到跟踪单元的跟踪位线预充电电路，其被配置为使用近端字线脉冲信号对与跟踪单元相关联的跟踪位线进行预充电。

公开(公告)号：US10304500B2

公开(公告)日：2019-05-28

申请号：US15902118

申请日：2018-02-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fu-An Wu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yu-Hao Hsu

IPC分类号： G11C5/14 ,  H03K17/687 ,  H03K17/22

摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

公开(公告)号：US20170040042A1

公开(公告)日：2017-02-09

申请号：US14980287

申请日：2015-12-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hektor Huang ,  Yangsyu Lin ,  Yu-Hao Hsu ,  Chia-En Huang ,  Chiting Cheng ,  Chen-Lin Yang ,  Jung-Ping Yang ,  Cheng Hung Lee

IPC分类号： G11C5/14 ,  H02J4/00

CPC分类号： G11C5/147 ,  H02J4/00

摘要： A power management circuit for an electronic device is disclosed that sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits. The power management circuit continues to sequentially provide each of the one or more circuit power management signals in a similar manner until the electronic circuits of the electronic device have been activated and/or deactivated.

摘要翻译： 公开了一种用于电子设备的电源管理电路，其顺序地激活和/或去激活电子设备的电子电路。 功率管理电路提供第一组一个或多个电路功率管理信号以激活和/或去激活来自电子电路之间的第一电子电路。 此后，电源管理电路从一个或多个电路电源管理信号的第二组中提供相应的功率管理信号，其对应于已经被第一组的第一组激活和/或去激活的第一电子电路的一部分 一个或多个电路功率管理信号，用于激活和/或去激活来自电子电路的第二电子电路的一部分。 功率管理电路以类似的方式继续顺序提供一个或多个电路功率管理信号中的每一个，直到电子设备的电子电路已经被激活和/或去激活为止。

公开(公告)号：US09111595B2

公开(公告)日：2015-08-18

申请号：US13904653

申请日：2013-05-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hao Hsu ,  Ming-Chien Tsai ,  Chen-Lin Yang

IPC分类号： G11C8/08 ,  G11C7/06 ,  G11C7/12 ,  G11C11/419 ,  G11C29/50 ,  G11C29/52

CPC分类号： G11C8/08 ,  G11C7/06 ,  G11C7/12 ,  G11C11/419 ,  G11C29/50 ,  G11C29/52

摘要： A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking wordline responsive to the first clock signal. The memory includes a tracking wordline level tuner for reducing a voltage level of a tracking wordline signal on the tracking wordline responsive to a weak bit control signal.

摘要翻译： 存储器包括响应于第二时钟信号和反馈信号提供第一时钟信号的时钟发生器。 反馈回路提供反馈信号，并且包括跟踪字线，跟踪位线，跟踪位单元和用于响应于第一时钟信号驱动跟踪字线的跟踪字线驱动器。 存储器包括跟踪字线电平调谐器，用于响应弱位控制信号减小跟踪字线上的跟踪字线信号的电压电平。

公开(公告)号：US20140307502A1

公开(公告)日：2014-10-16

申请号：US14316857

申请日：2014-06-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Lin Yang ,  Chung-Yi Wu ,  Yu-Hao Hsu

IPC分类号： G11C7/12 ,  G11C11/413

CPC分类号： G11C7/12 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

摘要： A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline row has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.

摘要翻译： 公开了一种字线跟踪电路和相应的方法，并且包括具有与之相关联的阻抗特性的跟踪字线，其对存储器件中的一行存储器单元进行建模，其中跟踪字线行具有近端，其接收具有 近端上升脉冲沿和近端下降脉冲沿。 跟踪字线也有一个远端。 跟踪单元组件耦合到接收字线脉冲信号的跟踪字线的远端。 最后，电路包括耦合到跟踪单元的跟踪位线预充电电路，其被配置为使用近端字线脉冲信号对与跟踪单元相关联的跟踪位线进行预充电。

公开(公告)号：US11675505B2

公开(公告)日：2023-06-13

申请号：US17717491

申请日：2022-04-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hao Hsu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Chiting Cheng ,  Fu-An Wu ,  Hung-Jen Liao ,  Jung-Ping Yang ,  Jonathan Tsung-Yung Chang ,  Wei Min Chan ,  Yen-Huei Chen ,  Yangsyu Lin ,  Chien-Chen Lin

IPC分类号： G06F3/06 ,  G11C5/14 ,  G11C11/4074 ,  G11C16/12 ,  G11C16/30 ,  H04B10/03 ,  H04B10/27 ,  H04J14/02

CPC分类号： G06F3/0625 ,  G06F3/0679 ,  G11C5/147 ,  G11C11/4074 ,  G11C16/12 ,  G11C16/30 ,  H04B10/03 ,  H04B10/27 ,  H04J14/0228 ,  H04J14/0268

摘要： Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.

公开(公告)号：US11301148B2

公开(公告)日：2022-04-12

申请号：US17201931

申请日：2021-03-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hao Hsu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Chiting Cheng ,  Fu-An Wu ,  Hung-Jen Liao ,  Jung-Ping Yang ,  Jonathan Tsung-Yung Chang ,  Wei Min Chan ,  Yen-Huei Chen ,  Yangsyu Lin ,  Chien-Chen Lin

IPC分类号： G11C5/14 ,  G06F3/06 ,  G11C11/4074 ,  G11C16/30 ,  G11C16/12 ,  H04B10/03 ,  H04B10/27 ,  H04J14/02

摘要： Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.

公开(公告)号：US10949100B2

公开(公告)日：2021-03-16

申请号：US16685722

申请日：2019-11-15

申请人： Taiwan Semiconductor Manufacturing Co. Ltd.

发明人： Yu-Hao Hsu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Chiting Cheng ,  Fu-An Wu ,  Hung-Jen Liao ,  Jung-Ping Yang ,  Jonathan Tsung-Yung Chang ,  Wei Min Chan ,  Yen-Huei Chen ,  Yangsyu Lin ,  Chien-Chen Lin

IPC分类号： G11C5/14 ,  G06F3/06 ,  G11C11/4074 ,  G11C16/30 ,  G11C16/12 ,  H04B10/03 ,  H04B10/27 ,  H04J14/02

摘要： Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.

公开(公告)号：US20200020363A1

公开(公告)日：2020-01-16

申请号：US16582029

申请日：2019-09-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fu-An Wu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yu-Hao Hsu

IPC分类号： G11C5/14 ,  H03K17/22 ,  H03K17/687

摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.