知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

23 records (took 0.022 seconds)

    METHOD FOR PROCESS VARIATION ANALYSIS OF AN INTEGRATED CIRCUIT
    3.
    发明申请
    METHOD FOR PROCESS VARIATION ANALYSIS OF AN INTEGRATED CIRCUIT 有权
    集成电路的变异分析方法

    公开(公告)号：US20150339414A1

    公开(公告)日：2015-11-26

    申请号：US14818349

    申请日：2015-08-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Cheng Kuo ,  Kmin Hsu ,  Wei-Yi Hu ,  Wei Min Chan ,  Jui-Feng Kuan

    IPC: G06F17/50 ,  G06F17/18

    CPC classification number: G06F17/18 ,  G06F17/5009 ,  G06F17/5036

    Abstract: A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values.

    Abstract translation: 提供了一种用于集成电路的工艺变化分析的方法和相应的系统。 生成描述集成电路的电子设备的网表在设备参数和过程参数方面。 过程参数包括对电子设备单独的本地过程参数和电子设备共同的全局过程参数。 识别关键电子设备具有对集成电路的设计规范的性能参数具有最大贡献的器件参数。 确定关键电子设备的全局过程参数和本地过程参数的灵敏度值。 灵敏度值表示一个或多个性能参数对关键电子设备的全局和局部过程参数的变化的敏感度。 蒙特卡罗（MC）样本根据灵敏度值进行排序。

    Power Line Lowering for Write Assisted Control Scheme
    5.
    发明申请
    Power Line Lowering for Write Assisted Control Scheme 有权
    电力线降低用于写辅助控制方案

    公开(公告)号：US20140133219A1

    公开(公告)日：2014-05-15

    申请号：US13674192

    申请日：2012-11-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

    Inventor： Wei-Cheng Wu ,  Wei Min Chan ,  Yen-Huei Chen ,  Hung-Jen Liao

    IPC: G11C5/14 ,  G11C11/419

    CPC classification number: G11C11/419

    Abstract: Some embodiments of the present disclosure relate to a memory array having a cell voltage generator configured to provide a cell voltage header to a plurality of memory cells. The cell voltage generator is connected to the memory cells by way of supply voltage line and controls a supply voltage of the memory cells. The cell voltage generator has a pull-down element coupled between a control node of the supply voltage line and a ground terminal, and a one or more pull-up elements connected in parallel between the control node and a cell voltage source. A control unit is configured to provide one or more variable valued pull-up enable signals to input nodes of the pull-up elements. The variable valued pull-up enable signals operate the pull-up elements to selectively connect the supply voltage line from the cell voltage source to provide a cell voltage header with a high slew rate.

    Abstract translation: 本公开的一些实施例涉及具有单元电压发生器的存储器阵列，其被配置为向多个存储器单元提供单元电压报头。 电池电压发生器通过电源电压线连接到存储器单元，并控制存储器单元的电源电压。 电池电压发生器具有耦合在电源电压线的控制节点和接地端子之间的下拉元件以及在控制节点和电池电压源之间并联连接的一个或多个上拉元件。 控制单元被配置为向上拉元件的输入节点提供一个或多个可变值上拉使能信号。 可变值上拉使能信号操作上拉元件以选择性地将电源电压线与电池电压源连接，以提供具有高压摆率的电池电压头。

    PRE-COLORED METHODOLOGY OF MULTIPLE PATTERNING
    7.
    发明申请
    PRE-COLORED METHODOLOGY OF MULTIPLE PATTERNING 审中-公开
    多彩图案的预色彩方法

    公开(公告)号：US20140068531A1

    公开(公告)日：2014-03-06

    申请号：US14076566

    申请日：2013-11-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Huei Chen ,  Wei Min Chan ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  G06F17/5068 ,  G06F2217/12

    Abstract: Some embodiments relate to a method for pre-coloring data within an integrated chip layout to avoid overlay errors that result from mask misalignment during multiple patterning lithography. The method may be performed by generating a graphical IC layout file containing an integrated chip layout having a plurality of IC shapes. The IC shapes within the graphical IC layout file are assigned a color during decomposition. The IC shapes are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. During mask building data associated with IC shapes that have been pre-colored is automatically sent to a same mask, regardless of the colors that are assigned to the shapes. Therefore, the pre-colored shapes are not assigned to a masked based upon a decomposition, but rather based upon the pre-coloring. By assigning IC shapes to a same mask through pre-coloring, overlay errors can be reduced.

    Abstract translation: 一些实施例涉及用于在集成芯片布局内预先着色数据的方法，以避免在多次图案化光刻期间由掩模未对准而产生的重叠误差。 该方法可以通过生成包含具有多个IC形状的集成芯片布局的图形IC布局文件来执行。 图形IC布局文件中的IC形状在分解过程中会分配一种颜色。 IC形状进一步预先着色，以故意将预色数据分配给相同的掩码。 在掩模建立过程中，与预先着色的IC形状相关联的数据将自动发送到相同的掩码，而不管分配给形状的颜色如何。 因此，预先着色的形状不是基于分解而分配给掩蔽的，而是基于预着色。 通过预先着色将IC形状分配给相同的掩模，可以减少重叠错误。

Patent Agency Ranking