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    METHOD OF FAILURE ANALYSIS
    2.
    发明申请
    METHOD OF FAILURE ANALYSIS 有权
    故障分析方法

    公开(公告)号：US20150089463A1

    公开(公告)日：2015-03-26

    申请号：US14492866

    申请日：2014-09-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Cheng Kuo ,  Kmin Hsu ,  Wei-Yi Hu ,  Wei Min Chan ,  Jui-Feng Kuan

    IPC: G06F17/50

    CPC classification number: G06F17/5009 ,  G06F17/5036

    Abstract: In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the IC model fails to meet a predetermined yield criteria. A simulation order for the number of input data sets is then assigned according to the determined number of scores.

    Abstract translation: 在一些方法中，为集成电路（IC）模型提供了许多输入数据集。 然后，分别基于输入数据集的概率确定输入数据集的数量的数量，导致当IC模型不能达到预定的收益准则时存在的故障条件。 然后根据确定的分数来分配输入数据集的数量的模拟顺序。

    Method for process variation analysis of an integrated circuit
    3.
    发明授权
    Method for process variation analysis of an integrated circuit 有权

    公开(公告)号：US09753895B2

    公开(公告)日：2017-09-05

    申请号：US14818349

    申请日：2015-08-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Cheng Kuo ,  Kmin Hsu ,  Wei-Yi Hu ,  Wei Min Chan ,  Jui-Feng Kuan

    IPC: G06F17/50 ,  G06F17/18

    CPC classification number: G06F17/18 ,  G06F17/5009 ,  G06F17/5036

    Abstract: A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values.

    Method of failure analysis
    5.
    发明授权
    Method of failure analysis 有权
    故障分析方法

    公开(公告)号：US09519735B2

    公开(公告)日：2016-12-13

    申请号：US14492866

    申请日：2014-09-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Cheng Kuo ,  Kmin Hsu ,  Wei-Yi Hu ,  Wei Min Chan ,  Jui-Feng Kuan

    IPC: G06F17/50

    CPC classification number: G06F17/5009 ,  G06F17/5036

    Abstract: In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the IC model fails to meet a predetermined yield criteria. A simulation order for the number of input data sets is then assigned according to the determined number of scores.

    Abstract translation: 在一些方法中，为集成电路（IC）模型提供了许多输入数据集。 然后，分别基于输入数据集的概率确定输入数据集的数量的数量，导致当IC模型不能达到预定的收益准则时存在的故障条件。 然后根据确定的分数来分配输入数据集的数量的模拟顺序。

    Method for integrated circuit design
    6.
    发明授权
    Method for integrated circuit design 有权

    公开(公告)号：US12204839B2

    公开(公告)日：2025-01-21

    申请号：US17719336

    申请日：2022-04-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tsun-Yu Yang ,  Ren-Hong Fu ,  Chin-Cheng Kuo ,  Jui-Feng Kuan

    IPC: G06F30/30 ,  G06F30/31 ,  G06F30/3308 ,  G06F30/392

    Abstract: A method is disclosed herein. The method includes: providing, by an electronic design automation (EDA), a trigger signal to an application programming interface (API); providing, by the API, first parameters associated with parameterized cells in a netlist of an integrated circuit (IC); adjusting, by the API, the first parameters to generate second parameters associated with the parameterized cells in the netlist of the IC; updating, by the API, the netlist of the IC according to the second parameters; and performing, by the EDA, a simulation according to the netlist.

    Variation-aware circuit simulation
    7.
    发明授权
    Variation-aware circuit simulation 有权

    公开(公告)号：US10169507B2

    公开(公告)日：2019-01-01

    申请号：US15439794

    申请日：2017-02-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Cheng Kuo ,  Wei-Yi Hu

    IPC: G06F17/50

    Abstract: An integration circuit (IC) simulation method includes: (a) providing a design netlist of a system-level circuit, wherein the system-level circuit comprises a first sub-circuit; (b) providing a first behavior model that is determined based on an operation of the first sub-circuit, wherein the first behavior model is a function of one or more respective behavior-level parameters; (c) incorporating a first variation into each of the one or more behavior-level parameters of the first behavioral model; and (d) simulating the system-level circuit based on the one or more behavior-level parameters of the first behavior model that incorporates the first variation.

    METHOD FOR PROCESS VARIATION ANALYSIS OF AN INTEGRATED CIRCUIT
    9.
    发明申请
    METHOD FOR PROCESS VARIATION ANALYSIS OF AN INTEGRATED CIRCUIT 有权
    集成电路的变异分析方法

    公开(公告)号：US20150339414A1

    公开(公告)日：2015-11-26

    申请号：US14818349

    申请日：2015-08-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Cheng Kuo ,  Kmin Hsu ,  Wei-Yi Hu ,  Wei Min Chan ,  Jui-Feng Kuan

    IPC: G06F17/50 ,  G06F17/18

    CPC classification number: G06F17/18 ,  G06F17/5009 ,  G06F17/5036

    Abstract: A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values.

    Abstract translation: 提供了一种用于集成电路的工艺变化分析的方法和相应的系统。 生成描述集成电路的电子设备的网表在设备参数和过程参数方面。 过程参数包括对电子设备单独的本地过程参数和电子设备共同的全局过程参数。 识别关键电子设备具有对集成电路的设计规范的性能参数具有最大贡献的器件参数。 确定关键电子设备的全局过程参数和本地过程参数的灵敏度值。 灵敏度值表示一个或多个性能参数对关键电子设备的全局和局部过程参数的变化的敏感度。 蒙特卡罗（MC）样本根据灵敏度值进行排序。

    Method and system for semiconductor simulation
    10.
    发明授权
    Method and system for semiconductor simulation 有权
    半导体仿真方法与系统

    公开(公告)号：US08707230B1

    公开(公告)日：2014-04-22

    申请号：US13792827

    申请日：2013-03-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Yi Hu ,  Chin-Cheng Kuo ,  Cheng-Hung Yeh ,  Jui-Feng Kuan ,  Yi-Kan Cheng

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F2217/10

    Abstract: An integrated circuit (IC) simulation method comprises providing a device process model from a non-transitory machine readable storage medium into a programmed computer. The device process model includes one or more device variables. Each device variable defines a probability distribution of an active-device-level variation of devices in an IC. A conductive line model and/or a multi patterning technology (MPT) model is provided from the storage medium to the computer. The conductive line model includes one or more conductive line variables. Each conductive line variable defines a probability distribution of a conductive-line process-induced variation. The MPT model includes one or more MPT variables. Each MPT variable defines a probability distribution of a mask-misalignment-induced conductive line coupling variation. A Monte Carlo simulation is performed in the computer, including the device process model and the conductive line model or MPT model, to identify parasitic couplings in the IC.

    Abstract translation: 集成电路（IC）模拟方法包括将设备处理模型从非暂时机器可读存储介质提供到编程计算机中。 设备过程模型包括一个或多个设备变量。 每个器件变量定义IC中器件的有源器件级变化的概率分布。 从存储介质向计算机提供导线模型和/或多图案形成技术（MPT）模型。 导线模型包括一个或多个导线变量。 每个导线变量定义了导线处理引起的变化的概率分布。 MPT模型包括一个或多个MPT变量。 每个MPT变量定义了掩模 - 未对准引起的导线耦合变化的概率分布。 在计算机中执行蒙特卡罗模拟，包括器件工艺模型和导线模型或MPT模型，以识别IC中的寄生耦合。

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