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    Integrated circuit with mixed row heights
    1.
    发明授权
    Integrated circuit with mixed row heights 有权

    公开(公告)号：US11282829B2

    公开(公告)日：2022-03-22

    申请号：US16883740

    申请日：2020-05-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kam-Tou Sio ,  Jiann-Tyng Tzeng ,  Chung-Hsing Wang ,  Yi-Kan Cheng

    IPC: H01L27/02 ,  H01L27/092 ,  G06F111/20

    Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

    Electromagnetic shielding metal-insulator-metal capacitor structure
    3.
    发明授权
    Electromagnetic shielding metal-insulator-metal capacitor structure 有权

    公开(公告)号：US10665550B2

    公开(公告)日：2020-05-26

    申请号：US16043355

    申请日：2018-07-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hui Yu Lee ,  Chin-Chou Liu ,  Cheng-Hung Yeh ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Ka Fai Chang

    IPC: H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  G06F17/50 ,  H01L23/522 ,  H01L27/02

    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

    Techniques based on electromigration characteristics of cell interconnect
    4.
    发明授权
    Techniques based on electromigration characteristics of cell interconnect 有权

    公开(公告)号：US10157254B2

    公开(公告)日：2018-12-18

    申请号：US15361970

    申请日：2016-11-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Nan Yang ,  Chung-Hsing Wang ,  Yi-Kan Cheng ,  Kumar Lalgudi

    IPC: G06F17/50 ,  H01L23/528 ,  H03K5/15

    Abstract: In some embodiments, the present disclosure relates to a clock tree structure disposed on a semiconductor substrate. The clock tree structure includes a first clock line having a first line width and being arranged at a first height as measured from an upper surface of the semiconductor substrate. The clock tree structure also includes a second clock line having a second line width, which differs from the first line width. The second clock line is arranged at a second height as measured from the upper surface of the semiconductor substrate and the second height is equal to the first height. The first line width can be directly proportional to a first current level for the first clock line and the second line width can be directly proportional to a second current level for the second clock line.

    Parasitic component library and method for efficient circuit design and simulation using the same
    5.
    发明授权
    Parasitic component library and method for efficient circuit design and simulation using the same 有权
    寄生元件库和方法用于高效电路设计和仿真使用

    公开(公告)号：US09348965B2

    公开(公告)日：2016-05-24

    申请号：US14542690

    申请日：2014-11-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Sheng Chen ,  Tsun-Yu Yang ,  Wei-Yi Hu ,  Tao Wen Chung ,  Jui-Feng Kuan ,  Yi-Kan Cheng

    IPC: G06F9/455 ,  G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5045

    Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

    Abstract translation: 一种用于电路设计的方法包括嵌入一个或多个参数化单元的寄生感知库。 寄生感知库用于将表示电路的一些但不是全部寄生效应的网络插入到电路原理图中，使单个电路原理图用于电路仿真，电路的寄生校验和LVS（布局与原理图）检查 。 电路设计过程只需要单一电路原理图，并形成掩模组。 识别单个电路原理图的关键路径，并提取寄生效应并将其插入原理图，使得能够执行寄生验证的预估计，并使用具有一些寄生效应的电路原理图进行LVS检查， 其中包括布局的所有寄生分量的后布局模拟。

    ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE
    10.
    发明申请
    ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE 有权

    公开(公告)号：US20210320072A1

    公开(公告)日：2021-10-14

    申请号：US17356039

    申请日：2021-06-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hui Yu LEE ,  Chin-Chou Liu ,  Cheng-Hung Yeh ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Ka Fai Chang

    IPC: H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398

    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

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