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    Must-Join Pin Sign-Off Method
    4.
    发明申请
    Must-Join Pin Sign-Off Method 审中-公开

    公开(公告)号：US20190155983A1

    公开(公告)日：2019-05-23

    申请号：US15908353

    申请日：2018-02-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Hsiung CHEN ,  Ming-Huei Tsai ,  Shao-Huan Wang ,  Shu-Yu Chen ,  Wen-Hao Chen ,  Chun-Chen Chen

    IPC: G06F17/50 ,  H01L21/67

    Abstract: The present disclosure describes a method for detecting unacceptable connection patterns. The method includes, using a processor to perform at least one of: performing an automated place-and-route (APR) process on a circuit layout that includes a first standard cell without a marker layer to generate a circuit graphic database system (GDS) file from the circuit layout, generating a standard-cell GDS file that includes a second standard cell with at least one marker layer applied to the second standard cell, and merging the circuit GDS file with the standard-cell GDS file to generate a merged GDS file that includes the first standard cell with at least one marker layer based on the second standard cell. The method further includes determining whether a connection pattern of the first standard cell in the merged GDS file is an unacceptable connection pattern.

    Layout for semiconductor device including via pillar structure
    5.
    发明授权
    Layout for semiconductor device including via pillar structure 有权

    公开(公告)号：US10289794B2

    公开(公告)日：2019-05-14

    申请号：US15616907

    申请日：2017-06-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Shao-Huan Wang ,  Sheng-Hsiung Chen ,  Wen-Hao Chen ,  Chun-Chen Chen ,  Hung-Chih Ou

    IPC: G06F17/50 ,  H01L23/522

    Abstract: A system is includes a processor and a computer readable medium. The computer readable medium connected to the processor. The computer readable medium is configured to store instructions. The processor is configured to execute the instructions for determining, according to at least one parameter of a cell in a semiconductor device indicated by a design file, a layout pattern indicating a via pillar structure that meets an electromigration (EM) rule. The via pillar structure comprises metal layers and at least one via, and the at least one via is coupled to the metal layers. The processor is further configured to execute the instructions for including, in the design file, the layout pattern indicating the via pillar structure. The processor is further configured to execute the instructions for generating data which indicate the design file, for fabrication of the semiconductor device.

    Standard Cells and Variations Thereof Within a Standard Cell Library
    6.
    发明申请
    Standard Cells and Variations Thereof Within a Standard Cell Library 审中-公开

    公开(公告)号：US20190064770A1

    公开(公告)日：2019-02-28

    申请号：US15800693

    申请日：2017-11-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Hsiung CHEN ,  Jerry Chang-Jui Kao ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Shao-Huan Wang ,  XinYong Wang ,  Yi-Kan Cheng ,  Chun-Chen Chen

    IPC: G05B19/4097 ,  G06F17/50 ,  H01L27/02

    Abstract: Exemplary embodiments for multiple standard cell libraries are disclosed that include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations have similar functionality as their one or more standard cells but are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for analog circuitry and/or digital circuitry of an electronic device. In an exemplary embodiment, a semiconductor foundry and/or semiconductor technology node can impose one or more electronic design constraints on the placement of the one or more standard cells onto an electronic device design real estate. In some situations, some of the one or more standard cells are unable to satisfy the one or more electronic design constraints when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

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