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公开(公告)号：US20240203997A1
公开(公告)日：2024-06-20
申请号：US18595049
申请日：2024-03-04
发明人： Fong-yuan Chang , Chun-Chen Chen , Po-Hsiang Huang , Lee-Chung Lu , Chung-Te Lin , Jerry Chang Jui Kao , Sheng-Hsiung Chen , Chin-Chou Liu
IPC分类号： H01L27/118 , G06F30/398 , H01L27/02
CPC分类号： H01L27/11807 , G06F30/398 , H01L27/0207 , H01L2027/11862 , H01L2027/11866 , H01L2027/11875 , H01L2027/11881 , H01L2027/11885
摘要： An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
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公开(公告)号：US11586797B2
公开(公告)日：2023-02-21
申请号：US17179904
申请日：2021-02-19
发明人： Fong-yuan Chang , Chin-Chou Liu , Chin-Her Chien , Cheng-Hung Yeh , Po-Hsiang Huang , Sen-Bor Jan , Yi-Kan Cheng , Hsiu-Chuan Shu
IPC分类号： G06F30/394 , G06F30/392 , G06F30/398
摘要： The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.
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公开(公告)号：US12056432B2
公开(公告)日：2024-08-06
申请号：US18300142
申请日：2023-04-13
发明人： Fong-yuan Chang , Chun-Chen Chen , Sheng-Hsiung Chen , Ting-Wei Chiang , Chung-Te Lin , Jung-Chan Yang , Lee-Chung Lu , Po-Hsiang Huang
IPC分类号： G06F30/30 , G06F30/392 , G06F30/394 , G06F30/398 , H01L27/02 , H01L27/118
CPC分类号： G06F30/398 , G06F30/392 , G06F30/394 , H01L27/0207 , H01L27/11807 , H01L2027/11875
摘要： The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.
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公开(公告)号：US11756951B2
公开(公告)日：2023-09-12
申请号：US17572296
申请日：2022-01-10
IPC分类号： H01L25/065 , H01L27/02 , H01L27/06 , G11C8/18 , H01L23/48
CPC分类号： H01L27/0207 , G11C8/18 , H01L23/481 , H01L25/0657 , H01L27/0688
摘要： A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.
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公开(公告)号：US11749584B2
公开(公告)日：2023-09-05
申请号：US17403485
申请日：2021-08-16
发明人： Po-Hsiang Huang , Chin-Chou Liu , Chin-Her Chien , Fong-yuan Chang , Hui Yu Lee
IPC分类号： H01L23/42 , H01L25/065 , H01L25/00 , H01L23/31 , H01L23/367
CPC分类号： H01L23/42 , H01L23/3128 , H01L23/3672 , H01L25/0657 , H01L25/50 , H01L2225/06541
摘要： The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.
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公开(公告)号：US10949597B2
公开(公告)日：2021-03-16
申请号：US16460137
申请日：2019-07-02
发明人： Fong-yuan Chang , Chin-Chou Liu , Chin-Her Chien , Cheng-Hung Yeh , Po-Hsiang Huang , Sen-Bor Jan , Yi-Kan Cheng , Hsiu-Chuan Shu
IPC分类号： G06F30/394 , G06F30/392 , G06F30/398
摘要： The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.
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公开(公告)号：US20230352366A1
公开(公告)日：2023-11-02
申请号：US18347013
申请日：2023-07-05
发明人： Po-Hsiang HUANG , Chin-chou Liu , Chin-Her Chien , Fong-yuan Chang , Hui Yu Lee
IPC分类号： H01L23/42 , H01L25/065 , H01L25/00 , H01L23/31 , H01L23/367
CPC分类号： H01L23/42 , H01L25/0657 , H01L25/50 , H01L23/3128 , H01L23/3672 , H01L2225/06541
摘要： The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.
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公开(公告)号：US11637098B2
公开(公告)日：2023-04-25
申请号：US17315900
申请日：2021-05-10
发明人： Fong-yuan Chang , Lee-Chung Lu , Po-Hsiang Huang , Chun-Chen Chen , Chung-Te Lin , Ting-Wei Chiang , Sheng-Hsiung Chen , Jung-Chan Yang
IPC分类号： H01L27/00 , H01L27/02 , H01L27/118 , G06F30/394 , G06F30/392
摘要： The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.
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公开(公告)号：US20220028842A1
公开(公告)日：2022-01-27
申请号：US17157520
申请日：2021-01-25
发明人： Fong-yuan Chang , Po-Hsiang Huang , Lee-Chung Lu , Jyh Chwen Frank Lee , Yii-Chian Lu , Yu-Hao Chen , Keh-Jeng Chang
IPC分类号： H01L25/10 , H01L23/367 , H01L23/31 , H01L23/538 , H01L23/00 , H01L25/065 , H01L21/48 , H01L21/56 , H01L21/683 , H01L25/00
摘要： A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.
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10.发明授权公开(公告)号：US11094608B2
公开(公告)日：2021-08-17
申请号：US16433967
申请日：2019-06-06
发明人： Po-Hsiang Huang , Chin-Chou Liu , Chin-Her Chien , Fong-yuan Chang , Hui Yu Lee
IPC分类号： H01L23/42 , H01L25/065 , H01L25/00 , H01L23/31 , H01L23/367
摘要： The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.
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