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    Electromagnetic shielding metal-insulator-metal capacitor structure
    2.
    发明授权
    Electromagnetic shielding metal-insulator-metal capacitor structure 有权

    公开(公告)号：US11088084B2

    公开(公告)日：2021-08-10

    申请号：US16863934

    申请日：2020-04-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hui Yu Lee ,  Chin-Chou Liu ,  Cheng-Hung Yeh ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Ka Fai Chang

    IPC: H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L27/02

    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

    Systems and methods for determining effective capacitance to facilitate a timing analysis
    3.
    发明授权
    Systems and methods for determining effective capacitance to facilitate a timing analysis 有权
    用于确定有效电容的系统和方法以促进时序分析

    公开(公告)号：US09104835B2

    公开(公告)日：2015-08-11

    申请号：US14562793

    申请日：2014-12-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-Yang Yeh ,  Cheng-Hung Yeh ,  Chi-Ting Huang

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5036

    Abstract: A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values.

    Abstract translation: 一种用于定时分析的方法包括使用处理器来确定至少第一级间通路（ILV）和第二ILV或器件之间的耦合的阻抗曲线，作为至少不同频率值的函数。 阻抗曲线包括对应于各个频率值的多个阻抗值。 确定对应于各个阻抗值的有效电容值。 为每个相应的频率值提供至少一个表，其具有相应的阻抗值和相应的有效电容值。 使用填充表并基于确定的有效电容值来进行ILV电路的设计布局的RC提取。

    Systems and methods for determining effective capacitance to facilitate a timing analysis
    6.
    发明授权
    Systems and methods for determining effective capacitance to facilitate a timing analysis 有权
    用于确定有效电容的系统和方法以促进时序分析

    公开(公告)号：US08910101B1

    公开(公告)日：2014-12-09

    申请号：US14051522

    申请日：2013-10-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-Yang Yeh ,  Cheng-Hung Yeh ,  Chi-Ting Huang

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5036 ,  H01L2224/73204

    Abstract: A method for determining an effective capacitance to facilitate a timing analysis using a processor generally comprises generating a model that is representative of a coupling between at least two TSVs. An impedance profile between the two TSVs as a function of at least one parameter is determined by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective values of the parameter. An effective capacitance value corresponding to each respective impedance value is determined. An RC extraction is conducted of a design layout of a TSV circuit based on each determined effective capacitance value to generate an RC network.

    Abstract translation: 用于确定有利电容以促进使用处理器的定时分析的方法通常包括生成代表至少两个TSV之间的耦合的模型。 通过使用该模型来确定作为至少一个参数的函数的两个TSV之间的阻抗曲线，其中阻抗分布包括对应于参数的相应值的多个阻抗值。 确定对应于各个阻抗值的有效电容值。 基于每个确定的有效电容值进行TSV电路的设计布局的RC提取以产生RC网络。

    Method and system for semiconductor simulation
    7.
    发明授权
    Method and system for semiconductor simulation 有权
    半导体仿真方法与系统

    公开(公告)号：US08707230B1

    公开(公告)日：2014-04-22

    申请号：US13792827

    申请日：2013-03-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Yi Hu ,  Chin-Cheng Kuo ,  Cheng-Hung Yeh ,  Jui-Feng Kuan ,  Yi-Kan Cheng

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F2217/10

    Abstract: An integrated circuit (IC) simulation method comprises providing a device process model from a non-transitory machine readable storage medium into a programmed computer. The device process model includes one or more device variables. Each device variable defines a probability distribution of an active-device-level variation of devices in an IC. A conductive line model and/or a multi patterning technology (MPT) model is provided from the storage medium to the computer. The conductive line model includes one or more conductive line variables. Each conductive line variable defines a probability distribution of a conductive-line process-induced variation. The MPT model includes one or more MPT variables. Each MPT variable defines a probability distribution of a mask-misalignment-induced conductive line coupling variation. A Monte Carlo simulation is performed in the computer, including the device process model and the conductive line model or MPT model, to identify parasitic couplings in the IC.

    Abstract translation: 集成电路（IC）模拟方法包括将设备处理模型从非暂时机器可读存储介质提供到编程计算机中。 设备过程模型包括一个或多个设备变量。 每个器件变量定义IC中器件的有源器件级变化的概率分布。 从存储介质向计算机提供导线模型和/或多图案形成技术（MPT）模型。 导线模型包括一个或多个导线变量。 每个导线变量定义了导线处理引起的变化的概率分布。 MPT模型包括一个或多个MPT变量。 每个MPT变量定义了掩模 - 未对准引起的导线耦合变化的概率分布。 在计算机中执行蒙特卡罗模拟，包括器件工艺模型和导线模型或MPT模型，以识别IC中的寄生耦合。

    Electromagnetic shielding metal-insulator-metal capacitor structure
    8.
    发明授权
    Electromagnetic shielding metal-insulator-metal capacitor structure 有权

    公开(公告)号：US10665550B2

    公开(公告)日：2020-05-26

    申请号：US16043355

    申请日：2018-07-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hui Yu Lee ,  Chin-Chou Liu ,  Cheng-Hung Yeh ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Ka Fai Chang

    IPC: H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  G06F17/50 ,  H01L23/522 ,  H01L27/02

    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

    ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE
    10.
    发明申请
    ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE 有权

    公开(公告)号：US20210320072A1

    公开(公告)日：2021-10-14

    申请号：US17356039

    申请日：2021-06-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hui Yu LEE ,  Chin-Chou Liu ,  Cheng-Hung Yeh ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Ka Fai Chang

    IPC: H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398

    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

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