公开(公告)号：US09646128B2

公开(公告)日：2017-05-09

申请号：US14705021

申请日：2015-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ashok Mehta ,  Stanley John ,  Kai-Yuan Ting ,  Sandeep Kumar Goel ,  Chao-Yang Yeh

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/50 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78

Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

公开(公告)号：US09104835B2

公开(公告)日：2015-08-11

申请号：US14562793

申请日：2014-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Yeh ,  Cheng-Hung Yeh ,  Chi-Ting Huang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5036

Abstract: A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values.

Abstract translation: 一种用于定时分析的方法包括使用处理器来确定至少第一级间通路（ILV）和第二ILV或器件之间的耦合的阻抗曲线，作为至少不同频率值的函数。 阻抗曲线包括对应于各个频率值的多个阻抗值。 确定对应于各个阻抗值的有效电容值。 为每个相应的频率值提供至少一个表，其具有相应的阻抗值和相应的有效电容值。 使用填充表并基于确定的有效电容值来进行ILV电路的设计布局的RC提取。

公开(公告)号：US20140183692A1

公开(公告)日：2014-07-03

申请号：US14144845

申请日：2013-12-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Yeh

IPC: H01L27/02 ,  G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5063

Abstract: Some methods provide an electronic design file, which includes an integrated circuit (IC) component that is operably coupled to a package component. The IC component and package component collectively form a resistor inductor capacitor (RLC) resonant circuit. The method also provides a damping component in the electronic design file. This damping component is configured to reduce a pre-resonant time during which energy exchanged in the RLC resonant circuit approaches a steady-state, and thereby speeds simulation time.

Abstract translation: 一些方法提供电子设计文件，其包括可操作地耦合到封装部件的集成电路（IC）组件。 IC组件和封装组件共同形成电阻电感电容（RLC）谐振电路。 该方法还在电子设计文件中提供阻尼分量。 该阻尼部件被配置为减少在RLC谐振电路中交换的能量接近稳态的预共振时间，从而加速模拟时间。

公开(公告)号：US11585831B2

公开(公告)日：2023-02-21

申请号：US16995866

申请日：2020-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mill-Jer Wang ,  Ching-Fang Chen ,  Sandeep Kumar Goel ,  Chung-Sheng Yuan ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee ,  Hung-Chih Lin

IPC: G01R1/07 ,  G01R1/073

Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

公开(公告)号：US20200379013A1

公开(公告)日：2020-12-03

申请号：US16995866

申请日：2020-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mill-Jer Wang ,  Ching-Fang Chen ,  Sandeep Kumar Goel ,  Chung-Sheng Yuan ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee ,  Hung-Chih Lin

IPC: G01R1/073

Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

公开(公告)号：US10782318B2

公开(公告)日：2020-09-22

申请号：US15789338

申请日：2017-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mill-Jer Wang ,  Ching-Fang Chen ,  Sandeep Kumar Goel ,  Chung-Sheng Yuan ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee ,  Hung-Chih Lin

IPC: G01R1/073

Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

公开(公告)号：US20180038894A1

公开(公告)日：2018-02-08

申请号：US15789338

申请日：2017-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mill-Jer Wang ,  Ching-Fang Chen ,  Sandeep Kumar Goel ,  Chung-Sheng Yuan ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee ,  Hung-Chih Lin

IPC: G01R1/073

CPC classification number: G01R1/07342 ,  G01R1/07378 ,  H01L2224/16225

Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

公开(公告)号：US09542517B2

公开(公告)日：2017-01-10

申请号：US14144845

申请日：2013-12-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Yeh

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5063

Abstract: Some methods provide an electronic design file, which includes an integrated circuit (IC) component that is operably coupled to a package component. The IC component and package component collectively form a resistor inductor capacitor (RLC) resonant circuit. The method also provides a damping component in the electronic design file. This damping component is configured to reduce a pre-resonant time during which energy exchanged in the RLC resonant circuit approaches a steady-state, and thereby speeds simulation time.

Abstract translation: 一些方法提供电子设计文件，其包括可操作地耦合到封装部件的集成电路（IC）部件。 IC组件和封装组件共同形成电阻电感电容（RLC）谐振电路。 该方法还在电子设计文件中提供阻尼分量。 该阻尼部件被配置为减少在RLC谐振电路中交换的能量接近稳态的预共振时间，从而加速模拟时间。

公开(公告)号：US09047432B2

公开(公告)日：2015-06-02

申请号：US13770158

申请日：2013-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ashok Mehta ,  Stanley John ,  Kai-Yuan Ting ,  Sandeep Kumar Goel ,  Chao-Yang Yeh

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/50 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78

Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

Abstract translation: 一种系统包括被配置为产生集成电路（IC）裸片的布局的由处理器实现的工具。 至少一个非暂时机器可读存储介质包括分别由第一和第二集成电路（IC）管芯上形成的第一和第二电路图案的第一栅极级描述编码的第一部分，以及用第 从处理器实现的工具接收的第一和第二电路图案的第二门级描述。 第二门级描述包括电源和接地端口，并且第一门级描述不包括电源和接地端口。 提供了一种处理器实现的第一验证模块，用于比较第一和第二门级描述并输出第一和第二电路图案的经验证的第二门级描述。

公开(公告)号：US08910101B1

公开(公告)日：2014-12-09

申请号：US14051522

申请日：2013-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Yeh ,  Cheng-Hung Yeh ,  Chi-Ting Huang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5036 ,  H01L2224/73204

Abstract: A method for determining an effective capacitance to facilitate a timing analysis using a processor generally comprises generating a model that is representative of a coupling between at least two TSVs. An impedance profile between the two TSVs as a function of at least one parameter is determined by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective values of the parameter. An effective capacitance value corresponding to each respective impedance value is determined. An RC extraction is conducted of a design layout of a TSV circuit based on each determined effective capacitance value to generate an RC network.

Abstract translation: 用于确定有利电容以促进使用处理器的定时分析的方法通常包括生成代表至少两个TSV之间的耦合的模型。 通过使用该模型来确定作为至少一个参数的函数的两个TSV之间的阻抗曲线，其中阻抗分布包括对应于参数的相应值的多个阻抗值。 确定对应于各个阻抗值的有效电容值。 基于每个确定的有效电容值进行TSV电路的设计布局的RC提取以产生RC网络。