公开(公告)号：US08910101B1

公开(公告)日：2014-12-09

申请号：US14051522

申请日：2013-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Yeh ,  Cheng-Hung Yeh ,  Chi-Ting Huang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5036 ,  H01L2224/73204

Abstract: A method for determining an effective capacitance to facilitate a timing analysis using a processor generally comprises generating a model that is representative of a coupling between at least two TSVs. An impedance profile between the two TSVs as a function of at least one parameter is determined by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective values of the parameter. An effective capacitance value corresponding to each respective impedance value is determined. An RC extraction is conducted of a design layout of a TSV circuit based on each determined effective capacitance value to generate an RC network.

Abstract translation: 用于确定有利电容以促进使用处理器的定时分析的方法通常包括生成代表至少两个TSV之间的耦合的模型。 通过使用该模型来确定作为至少一个参数的函数的两个TSV之间的阻抗曲线，其中阻抗分布包括对应于参数的相应值的多个阻抗值。 确定对应于各个阻抗值的有效电容值。 基于每个确定的有效电容值进行TSV电路的设计布局的RC提取以产生RC网络。

公开(公告)号：US09104835B2

公开(公告)日：2015-08-11

申请号：US14562793

申请日：2014-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Yeh ,  Cheng-Hung Yeh ,  Chi-Ting Huang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5036

Abstract: A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values.

Abstract translation: 一种用于定时分析的方法包括使用处理器来确定至少第一级间通路（ILV）和第二ILV或器件之间的耦合的阻抗曲线，作为至少不同频率值的函数。 阻抗曲线包括对应于各个频率值的多个阻抗值。 确定对应于各个阻抗值的有效电容值。 为每个相应的频率值提供至少一个表，其具有相应的阻抗值和相应的有效电容值。 使用填充表并基于确定的有效电容值来进行ILV电路的设计布局的RC提取。

公开(公告)号：US09330215B2

公开(公告)日：2016-05-03

申请号：US14219029

申请日：2014-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Hsien Tsai ,  Chi-Ting Huang ,  Cheng-Hung Yeh ,  Hsien-Hsin Sean Lee

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/504 ,  G06F17/5081 ,  G06F2217/82

Abstract: A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic (“LVS”) check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.

Abstract translation: 一种用于验证具有多个层的IC的设计的方法包括进行布局与示意图（“LVS”）检查以分离多个设计布局中的多个设备，其中每个设计布局对应于具有 各自的设备。 使用计算设备在彼此的不同层中的一个设备之间生成多个相邻层连接。 执行每个层的第一RC提取以计算相应设计布局的多个设备中的每一个之间的耦合。 执行每个相邻层连接的第二RC提取。