公开(公告)号：US11545298B2

公开(公告)日：2023-01-03

申请号：US17169118

申请日：2021-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ka Fai Chang ,  Chin-Chou Liu ,  Fong-Yuan Chang ,  Hui Yu Lee ,  Yi-Kan Cheng

IPC: H01L27/08 ,  H01F27/34 ,  H01F27/28 ,  H01F41/04 ,  H01L49/02 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48

Abstract: An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.

公开(公告)号：US11749584B2

公开(公告)日：2023-09-05

申请号：US17403485

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsiang Huang ,  Chin-Chou Liu ,  Chin-Her Chien ,  Fong-yuan Chang ,  Hui Yu Lee

IPC: H01L23/42 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L23/42 ,  H01L23/3128 ,  H01L23/3672 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

公开(公告)号：US11694973B2

公开(公告)日：2023-07-04

申请号：US17356039

申请日：2021-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Yu Lee ,  Chin-Chou Liu ,  Cheng-Hung Yeh ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Ka Fai Chang

IPC: H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L27/02

CPC classification number: H01L23/552 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L23/49822 ,  H01L23/5223 ,  H01L28/60 ,  H01L27/0207

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

公开(公告)号：US20220375827A1

公开(公告)日：2022-11-24

申请号：US17875199

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Chin-Chou Liu ,  Chin-Her Chien ,  Cheny-hung Yeh ,  Hui Yu Lee ,  Po-Hsiang Huang ,  Yi-Kan Cheng

IPC: H01L23/48 ,  H01L23/00 ,  H01L27/06

Abstract: A device, such as a computer system, includes an interconnection device die and at least two additional device dice. The additional device dies can be system on integrated chip (SOIC) dies laying face to face (F2F) on the interconnection device die. The interconnection device die includes electrical connectors on one surface, enabling connection to and/or among the additional device dice. The interconnection device die includes at least one redistribution circuit structure, which may be an integrated fan out (InFO) structure, and at least one through-silicon via (TSV). The TSV enables connection between a signal line, power line or ground line, from an opposite surface of the interconnection device die to the redistribution circuit structure and/or electrical connectors. At least one of the additional dice can be a three-dimensional integrated circuit (3DIC) die with face to back (F2B) stacking.

公开(公告)号：US10467375B2

公开(公告)日：2019-11-05

申请号：US15697206

申请日：2017-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Yu Lee ,  Hao-Tien Kan

IPC: G06F17/50

Abstract: A method includes providing a symbolic power distribution network (PDN) map for a PDN of an circuit design including at least a first mesh that includes a plurality of map nodes; modeling at least one parasitic component that is provided on a branch of the symbolic PDN map and a pair of current sources that are provided at two respective map nodes of the symbolic PDN map; providing a matrix equation based on an interrelated conduction behavior among the parasitic component and the pair of current sources, wherein the matrix equation includes a current source term representing the pair of current sources and an unknown variable term representing a voltage level of at least a map node of the symbolic PDN map; and based on the matrix equation, expanding the unknown variable term in a frequency-domain as a sum of plural mathematical components while keeping the current source term intact.

公开(公告)号：US10192833B2

公开(公告)日：2019-01-29

申请号：US14943063

申请日：2015-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Feng-Wei Kuo ,  Hui Yu Lee ,  Huan-Neng Chen ,  Yen-Jen Chen ,  Yu-Ling Lin ,  Chewn-Pu Jou

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/66 ,  H01L23/14 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/64 ,  H01L25/065

Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.

公开(公告)号：US09219039B2

公开(公告)日：2015-12-22

申请号：US14018634

申请日：2013-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Wei Kuo ,  Hui Yu Lee ,  Huan-Neng Chen ,  Yen-Jen Chen ,  Yu-Ling Lin ,  Chewn-Pu Jou

IPC: H01L23/552 ,  H01L23/538 ,  H01L23/14 ,  H01L23/00 ,  H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/642 ,  H01L23/66 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/014

Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.

Abstract translation: 插入器和半导体封装实施例提供了隔离和抑制电子噪声，例如半导体封装中的EM发射。 插入器包括各种实施例中的屏蔽结构，屏蔽结构阻挡来自噪声源的电噪声与其它电信号或装置。 在其他实施例中，屏蔽件包括固体结构和一些实施例以及去耦电容器。 耦合结构包括多个包含在条中的焊球，其耦合部件并围绕并包含电噪声源。

公开(公告)号：US11088084B2

公开(公告)日：2021-08-10

申请号：US16863934

申请日：2020-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Yu Lee ,  Chin-Chou Liu ,  Cheng-Hung Yeh ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Ka Fai Chang

IPC: H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L27/02

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

公开(公告)号：US09335624B2

公开(公告)日：2016-05-10

申请号：US14277108

申请日：2014-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Yu Lee ,  Chi-Wen Chang ,  Chih Ming Yang ,  Ya Yun Liu ,  Yi-Kan Cheng

IPC: G06F17/50 ,  G03F1/00

CPC classification number: G03F1/00 ,  G03F1/144 ,  G03F1/70 ,  G03F7/70466 ,  G06F17/5068 ,  G06F17/5081

Abstract: A non-transitory, computer readable storage medium is encoded with computer program instructions, such that, when the computer program instructions are executed by a computer, the computer performs a method. The method generates mask assignment information for forming a plurality of patterns on a layer of an integrated circuit (IC) by multipatterning. The mask assignment information includes, for each of the plurality of patterns, a mask assignment identifying which of a plurality of masks is to be used to form that pattern, and a mask assignment lock state for that pattern. User inputs setting the mask assignment of at least one of the plurality of patterns, and its mask assignment lock state are received. A new mask assignment is generated for each of the plurality of patterns having an “unlocked” mask assignment lock state.

Abstract translation: 非暂时的计算机可读存储介质用计算机程序指令编码，使得当计算机程序指令由计算机执行时，计算机执行方法。 该方法通过多图案产生用于在集成电路（IC）的层上形成多个图案的掩模分配信息。 对于多个图案中的每一个，掩模分配信息包括识别多个掩模中哪一个要用于形成该图案的掩模分配以及该图案的掩模分配锁定状态。 用户输入设置多个图案中的至少一个的掩模分配以及其掩码分配锁定状态。 为具有“未锁定”掩码分配锁定状态的多个图案中的每一个生成新的掩模分配。

公开(公告)号：US10971485B2

公开(公告)日：2021-04-06

申请号：US16283017

申请日：2019-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Yu Lee ,  Ka Fai Chang

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/64 ,  H01L23/48 ,  H01L23/31 ,  H01L23/522 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

Abstract: An exemplary multi-chip package includes one or more solenoid inductors. An exemplary enclosing IC package includes one or more electrical interconnections propagating throughout which can be arranged to form a first solenoid inductor situated within the exemplary multi-chip package. Moreover, the exemplary enclosing IC package can be connected to an exemplary enclosed IC package to form the exemplary multi-chip package. The exemplary enclosed IC package can include a second solenoid inductor formed therein. Furthermore, the exemplary enclosing IC package can include a first portion of a third solenoid inductor and the exemplary enclosed IC package can include a second portion of the third solenoid inductor. The exemplary enclosed IC package can be connected to the exemplary enclosing IC package to connect the first portion of the third solenoid inductor and the second portion of the third solenoid inductor to form the third solenoid inductor.