Invention Grant
- Patent Title: Method of failure analysis
- Patent Title (中): 故障分析方法
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Application No.: US14492866Application Date: 2014-09-22
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Publication No.: US09519735B2Publication Date: 2016-12-13
- Inventor: Chin-Cheng Kuo , Kmin Hsu , Wei-Yi Hu , Wei Min Chan , Jui-Feng Kuan
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the IC model fails to meet a predetermined yield criteria. A simulation order for the number of input data sets is then assigned according to the determined number of scores.
Public/Granted literature
- US20150089463A1 METHOD OF FAILURE ANALYSIS Public/Granted day:2015-03-26
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