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公开(公告)号：US20240274555A1
公开(公告)日：2024-08-15
申请号：US18313746
申请日：2023-05-08
发明人： Wei-Jen Lo , Syun-Ming Jang , Ming-Hsing Tsai , Chun-Chieh Lin , Hung-Wen Su , Ya-Lien Lee , Chih-Han Tseng , Chih-Cheng Kuo , Yi-An Lai , Kevin Huang , Kuan-Hung Ho
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/0239 , H01L2224/0384 , H01L2224/05073 , H01L2224/05184 , H01L2224/05582
摘要： Embodiments provide a method and resulting structure that includes forming an opening in a dielectric layer to expose a metal feature, selectively depositing a metal cap on the metal feature, depositing a barrier layer over the metal cap, and depositing a conductive fill on the barrier layer.
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公开(公告)号：US20230282729A1
公开(公告)日：2023-09-07
申请号：US17662545
申请日：2022-05-09
发明人： Hsin-Yi Lee , Chun-Da Liao , Cheng-Lung Hung , Yan-Ming Tsai , Harry Chien , Huang-Lin Chao , Weng Chang , Chih-Wei Chang , Ming-Hsing Tsai , Chi On Chui
IPC分类号： H01L29/66 , H01L29/06 , H01L29/423
CPC分类号： H01L29/66545 , H01L29/0665 , H01L29/42392 , H01L29/66795 , H01L29/41791
摘要： A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, forming a gate dielectric layer extending into the trench and on the semiconductor region, and depositing a fist work-function layer over the gate dielectric layer. The work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum, and combinations thereof. The method further includes depositing a conductive filling layer over the first work-function layer, and performing a planarization process to remove excess portions of the conductive filling layer, the first work-function layer, and the gate dielectric layer to form a gate stack.
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3.发明授权公开(公告)号：US11222818B2
公开(公告)日：2022-01-11
申请号：US16034843
申请日：2018-07-13
发明人： Yi-Hsiang Chao , Min-Hsiu Hung , Chun-Wen Nieh , Ya-Huei Li , Yu-Hsiang Liao , Li-Wei Chu , Kan-Ju Lin , Kuan-Yu Yeh , Chi-Hung Chuang , Chih-Wei Chang , Ching-Hwanq Su , Hung-Yi Huang , Ming-Hsing Tsai
IPC分类号： H01L23/00 , H01L21/768 , H01L29/78 , H01L29/08 , H01L29/06 , H01L29/45 , H01L21/324 , H01L29/66 , H01L21/285 , H01L21/265 , H01L23/535
摘要： A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
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公开(公告)号：US11195791B2
公开(公告)日：2021-12-07
申请号：US16707301
申请日：2019-12-09
发明人： Yu-Wen Cheng , Wei-Yip Loh , Yu-Hsiang Liao , Sheng-Hsuan Lin , Hong-Mao Lee , Chun-I Tsai , Ken-Yu Chang , Wei-Jung Lin , Chih-Wei Chang , Ming-Hsing Tsai
IPC分类号： H01L21/768 , H01L23/522 , H01L29/66 , H01L21/285 , H01L21/8238 , H01L23/498 , H01L23/00 , H01L21/48
摘要： A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.
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公开(公告)号：US20210272910A1
公开(公告)日：2021-09-02
申请号：US17306784
申请日：2021-05-03
发明人： Wen-Jiun LIU , Chen-Yuan Kao , Hung-Wen Su , Ming-Hsing Tsai , Syun-Ming Jang
IPC分类号： H01L23/532 , H01L21/768 , H01L21/288 , H01L23/528 , H01L21/3105 , H01L21/311 , H01L21/3213 , H01L23/522
摘要： A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.
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公开(公告)号：US20200152763A1
公开(公告)日：2020-05-14
申请号：US16740881
申请日：2020-01-13
发明人： Yu-Wen Cheng , Cheng-Tung Lin , Chih-Wei Chang , Hong-Mao Lee , Ming-Hsing Tsai , Sheng-Hsuan Lin , Wei-Jung Lin , Yan-Ming Tsai , Yu-Shiuan Wang , Hung-Hsu Chen , Wei-Yip Loh , Ya-Yi Cheng
IPC分类号： H01L29/66 , H01L29/08 , H01L21/768 , H01L29/78 , H01L21/02 , H01L21/326 , H01L29/45
摘要： Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
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公开(公告)号：US09824969B1
公开(公告)日：2017-11-21
申请号：US15154989
申请日：2016-05-14
发明人： Chung-Chiang Wu , Chia-Ching Lee , Hsueh-Wen Tsau , Chun-Yuan Chou , Cheng-Yen Tsai , Da-Yuan Lee , Ming-Hsing Tsai
IPC分类号： H01L23/52 , H01L21/4763 , H01L21/44 , H01L29/66 , H01L23/528 , H01L21/311 , H01L21/768 , H01L23/532 , H01L29/49
CPC分类号： H01L23/528 , H01L21/31133 , H01L21/31138 , H01L21/76861 , H01L21/76879 , H01L23/485 , H01L23/53228 , H01L23/53257 , H01L23/53261 , H01L29/4966
摘要： A semiconductor structure and the method of forming the same are provided. The method of forming a semiconductor structure includes forming a recess feature in a basal layer, forming a metal layer on the basal layer, exposing the metal layer to a tungsten halide gas to form an oxygen-deficient metal layer, and forming a bulk tungsten layer on the oxygen-deficient metal layer.
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公开(公告)号：US20230268228A1
公开(公告)日：2023-08-24
申请号：US18308743
申请日：2023-04-28
发明人： Ken-Yu Chang , Chun-I Tsai , Ming-Hsing Tsai , Wei-Jung Lin
IPC分类号： H01L21/768 , H01L29/66 , H01L21/8234 , H01L21/67
CPC分类号： H01L21/76846 , H01L21/67075 , H01L21/76877 , H01L21/823418 , H01L21/823475 , H01L29/66545
摘要： Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.
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公开(公告)号：US20230260836A1
公开(公告)日：2023-08-17
申请号：US17663315
申请日：2022-05-13
发明人： Pei Shan Chang , Yi-Hsiang Chao , Chun-Hsien Huang , Peng-Hao Hsu , Kevin Lee , Shu-Lan Chang , Ya-Yi Cheng , Ching-Yi Chen , Wei-Jung Lin , Chih-Wei Chang , Ming-Hsing Tsai
IPC分类号： H01L21/768 , H01L29/786 , H01L29/06 , H01L29/66 , H01L21/8234
CPC分类号： H01L21/76852 , H01L29/78618 , H01L29/0665 , H01L29/78696 , H01L29/66742 , H01L21/823418 , H01L21/76876
摘要： A method includes forming a dielectric layer over a source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source/drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.
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公开(公告)号：US11552018B2
公开(公告)日：2023-01-10
申请号：US17306784
申请日：2021-05-03
发明人： Wen-Jiun Liu , Chen-Yuan Kao , Hung-Wen Su , Ming-Hsing Tsai , Syun-Ming Jang
IPC分类号： H01L23/532 , H01L21/768 , H01L21/288 , H01L23/528 , H01L21/3105 , H01L21/311 , H01L21/3213 , H01L23/522
摘要： A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.
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