公开(公告)号：US20230282729A1

公开(公告)日：2023-09-07

申请号：US17662545

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Chun-Da Liao ,  Cheng-Lung Hung ,  Yan-Ming Tsai ,  Harry Chien ,  Huang-Lin Chao ,  Weng Chang ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/41791

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, forming a gate dielectric layer extending into the trench and on the semiconductor region, and depositing a fist work-function layer over the gate dielectric layer. The work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum, and combinations thereof. The method further includes depositing a conductive filling layer over the first work-function layer, and performing a planarization process to remove excess portions of the conductive filling layer, the first work-function layer, and the gate dielectric layer to form a gate stack.