公开(公告)号：US11676866B2

公开(公告)日：2023-06-13

申请号：US17334848

申请日：2021-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Kuo-Cheng Ching ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu

IPC: H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823462 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/66795 ,  H01L29/517 ,  H01L29/518

Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

公开(公告)号：US09947773B2

公开(公告)日：2018-04-17

申请号：US14326746

申请日：2014-07-09

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Carlos H. Diaz

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78696

Abstract: One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel, such as an un-doped channel, over a substrate. The semiconductor arrangement comprises a gate, such as a gate-all-around structure gate, around the channel. The semiconductor arrangement comprises an isolation structure, such as a silicon germanium oxide structure, between the gate and the substrate. The isolation structure blocks current leakage into the substrate. Because the semiconductor arrangement comprises the isolation structure, the channel can be left un-doped, which improves electron mobility and decreases gate capacitance.

公开(公告)号：US09640645B2

公开(公告)日：2017-05-02

申请号：US14018737

申请日：2013-09-05

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/775 ,  H01L29/786 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/06 ,  H01L29/41 ,  H01L29/16

CPC classification number: H01L29/41741 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28518 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/413 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78642

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.

公开(公告)号：US09406778B2

公开(公告)日：2016-08-02

申请号：US14461502

申请日：2014-08-18

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Guan-Lin Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a doped region, in some embodiments. The semiconductor device includes a gate over a channel portion of the fin. The gate including a gate electrode over a gate dielectric between a first sidewall spacer and a second sidewall spacer. The first sidewall spacer includes an initial first sidewall spacer over a first portion of a dielectric material. The second sidewall spacer includes an initial second sidewall spacer over a second portion of the dielectric material.

Abstract translation: 本文提供半导体器件和形成方法。 在一些实施例中，半导体器件包括具有掺杂区域的鳍。 半导体器件包括在鳍的通道部分上的栅极。 栅极包括在第一侧壁间隔物和第二侧壁间隔物之间​​的栅电介质上的栅电极。 第一侧壁间隔物包括介电材料的第一部分上的初始第一侧壁间隔物。 第二侧壁间隔物包括在电介质材料的第二部分上的初始第二侧壁间隔物。

公开(公告)号：US20150048441A1

公开(公告)日：2015-02-19

申请号：US13969114

申请日：2013-08-16

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/78 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/32139 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775

Abstract: A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm.

Abstract translation: 半导体装置包括从衬底区域突出的衬底区域和第一半导体柱。 半导体装置包括从基板区域突出的第二半导体柱。 第二半导体柱与第一半导体柱分开第一距离。 第一距离在约10nm至约30nm之间。

公开(公告)号：US10699964B2

公开(公告)日：2020-06-30

申请号：US16205419

申请日：2018-11-30

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Carlos H. Diaz ,  Jean-Pierre Colinge

IPC: H01L21/8238 ,  H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L27/092 ,  H01L29/16

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

公开(公告)号：US10290737B2

公开(公告)日：2019-05-14

申请号：US15983444

申请日：2018-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L21/308 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L21/3213

Abstract: A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm.

公开(公告)号：US09881993B2

公开(公告)日：2018-01-30

申请号：US14317069

申请日：2014-06-27

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Carlos H. Diaz

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/167 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/267

CPC classification number: H01L29/0615 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/167 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor device having a horizontal gate all around structure on a bulk substrate is provided. The method comprises forming a plurality of fins on a bulk substrate wherein each fin comprises a vertical slice of substrate material and a plurality of channel layers above the vertical slice of substrate material. The plurality of channel layers includes a top channel layer above a bottom channel layer. Each channel layer comprises a first sublayer of removable semiconductor material overlaid by a second sublayer of semiconductor material. The method further comprises providing shallow trench isolation (STI) material between the vertical slices of the bulk substrate in the plurality of fins, depositing poly material around a central portion of the plurality of fins, forming source and drain regions, and forming an interlayer dielectric layer (ILD0). The method also comprises removing the poly material, forming a plurality of channels from the channel layers, and forming a gate around the channels.

公开(公告)号：US20150200300A1

公开(公告)日：2015-07-16

申请号：US14155793

申请日：2014-01-15

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Zhiqiang Wu ,  Carlos H. Diaz

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/76224 ,  H01L21/76235 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFet, as compared to a FinFet including fins that do not include a dielectric disposed within a furrow.

Abstract translation: 本文提供半导体器件和形成方法。 半导体器件包括具有沿着第一平面延伸的第一壁的鳍片，鳍片包括在第一平面的第一侧上限定第一沟槽的掺杂区域。 电介质设置在第一沟槽内，使得电介质与电介质的第一端和电介质的第二端之间的第一沟槽接触。 第一端与第一平面分开第一距离。 与包括不包括设置在沟槽内的电介质的翅片的FinFet相比，设置在沟槽内的电介质增加了相邻散热片的通道部分的隔离，从而减小了FinFet的漏电流。

公开(公告)号：US20150060996A1

公开(公告)日：2015-03-05

申请号：US14018737

申请日：2013-09-05

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41741 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28518 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/413 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78642

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.

Abstract translation: 半导体器件包括包括第一导电类型的第一类型区域。 半导体器件包括包括第二导电类型的第二类型区域。 半导体器件包括在第一类型区域和第二类型区域之间延伸的沟道区域。 半导体器件包括在第一类型区域的第一类型表面区域上的第一硅化物区域。 第一硅化物区域与第一类型区域的第一类型扩散区域的第一距离或距沟道区域的第二距离中的至少一个分离。