公开(公告)号：US20220181250A1

公开(公告)日：2022-06-09

申请号：US17676300

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Li-Zhen YU ,  Chia-Hao Chang ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L29/423 ,  H01L21/768 ,  H01L23/535 ,  H01L29/45 ,  H01L29/786

Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

公开(公告)号：US11239340B2

公开(公告)日：2022-02-01

申请号：US16895062

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Tai-I Yang ,  Tien-Lu Lin ,  Wai-Yi Lien ,  Chih-Hao Wang ,  Jiun-Peng Wu

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L21/4757 ,  H01L29/40

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.

公开(公告)号：US20220013653A1

公开(公告)日：2022-01-13

申请号：US16926258

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Yi-Ruei Jhan ,  Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/165

Abstract: A semiconductor device includes a first active fin structure and a second active fin structure extending along a first lateral direction. The semiconductor device includes a dummy fin structure, also extending along the first lateral direction, that is disposed between the first active fin structure and the second fin structure. The dummy fin structure includes a material that is configured to induce mechanical deformation of a first source/drain structure coupled to an end of the first active fin structure and a second source/drain structure coupled to an end of the second active fin structure.

公开(公告)号：US11217676B1

公开(公告)日：2022-01-04

申请号：US16910120

申请日：2020-06-24

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Che-Chen Wu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Jia-Chuan You ,  Li-Yang Chuang

IPC: H01L21/311 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A gate-all-around field effect transistor may be provided by forming a sacrificial gate structure and a dielectric gate spacer around a middle portion of a semiconductor plate stack. A source region and a drain region may be formed on end portions of semiconductor plates within the semiconductor plate stack. The sacrificial gate structure and other sacrificial material portions may be replaced with a combination of a gate dielectric layer and a gate electrode. The gate dielectric layer and the gate electrode may be vertically recessed selective to the dielectric gate spacer. A first anisotropic etch process recesses the gate electrode and the gate dielectric layer at about the same etch rate. A second anisotropic etch process with a higher selectivity may be subsequently used. Protruding remaining portions of the gate dielectric layer are minimized to reduce leakage current between adjacent transistors.

公开(公告)号：US10294101B2

公开(公告)日：2019-05-21

申请号：US15705359

申请日：2017-09-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Jean-Pierre Colinge ,  Ta-Pen Guo ,  Chih-Hao Wang ,  Carlos H. Diaz

IPC: H01L21/308 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor arrangement includes a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement includes a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The second semiconductor column is separated a first distance from the first semiconductor column along a first axis. The semiconductor arrangement includes a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The third semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis. The second distance is different than the first distance.

公开(公告)号：US09947773B2

公开(公告)日：2018-04-17

申请号：US14326746

申请日：2014-07-09

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Carlos H. Diaz

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78696

Abstract: One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel, such as an un-doped channel, over a substrate. The semiconductor arrangement comprises a gate, such as a gate-all-around structure gate, around the channel. The semiconductor arrangement comprises an isolation structure, such as a silicon germanium oxide structure, between the gate and the substrate. The isolation structure blocks current leakage into the substrate. Because the semiconductor arrangement comprises the isolation structure, the channel can be left un-doped, which improves electron mobility and decreases gate capacitance.

公开(公告)号：US09755033B2

公开(公告)日：2017-09-05

申请号：US14303744

申请日：2014-06-13

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Chih-Hao Wang ,  Wai-Yi Lien ,  Shi-Ning Ju ,  Kai-Chieh Yang ,  Wen-Ting Lan

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/7827

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

公开(公告)号：US12100656B2

公开(公告)日：2024-09-24

申请号：US18335175

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Li-Zhen Yu ,  Chia-Hao Chang ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L23/528 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/78696

Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

公开(公告)号：US20230275154A1

公开(公告)日：2023-08-31

申请号：US18312666

申请日：2023-05-05

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Li-Zhen Yu ,  Chia-Hao Chang ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L29/49

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/66795 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/4975 ,  H01L2029/7858

Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

公开(公告)号：US11721623B2

公开(公告)日：2023-08-08

申请号：US17676300

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Li-Zhen Yu ,  Chia-Hao Chang ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/00 ,  H01L23/528 ,  H01L29/423 ,  H01L21/768 ,  H01L23/535 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L23/528 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/78696

Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.