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公开(公告)号：US11682730B2
公开(公告)日：2023-06-20
申请号：US16910125
申请日：2020-06-24
Inventor： Li-Zhen Yu , Chia-Hao Chang , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC: H01L29/78 , H01L29/417 , H01L29/423 , H01L29/66 , H01L23/522 , H01L23/528 , H01L29/49
CPC classification number: H01L29/785 , H01L23/528 , H01L23/5226 , H01L29/41791 , H01L29/42372 , H01L29/4975 , H01L29/66795 , H01L2029/7858
Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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公开(公告)号：US11637064B2
公开(公告)日：2023-04-25
申请号：US17098717
申请日：2020-11-16
Inventor： Chih-Liang Chen , Cheng-Chi Chuang , Chih-Ming Lai , Chia-Tien Wu , Charles Chew-Yuen Young , Hui-Ting Yang , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Shun Li Chen , Shih-Wei Peng , Tien-Lu Lin
IPC: H01L23/528 , H01L21/768 , H01L23/522 , H01L27/02 , H01L29/49
Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
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公开(公告)号：US11257758B2
公开(公告)日：2022-02-22
申请号：US16910453
申请日：2020-06-24
Inventor： Li-Zhen Yu , Chia-Hao Chang , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC: H01L21/00 , H01L23/528 , H01L29/423 , H01L21/768 , H01L23/535 , H01L29/45 , H01L29/786
Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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公开(公告)号：US20200020625A1
公开(公告)日：2020-01-16
申请号：US16581833
申请日：2019-09-25
Inventor： Chih-Liang Chen , Cheng-Chi Chuang , Chih-Ming Lai , Chia-Tien Wu , Charles Chew-Yuen Young , Hui-Ting Yang , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Shun Li Chen , Shih-Wei Peng , Tien-Lu Lin
IPC: H01L23/528 , H01L29/49 , H01L27/02 , H01L23/522 , H01L21/768
Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
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公开(公告)号：US20230326851A1
公开(公告)日：2023-10-12
申请号：US18335175
申请日：2023-06-15
Inventor： Li-Zhen Yu , Chia-Hao Chang , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC: H01L23/528 , H01L29/423 , H01L21/768 , H01L23/535 , H01L29/45 , H01L29/786
CPC classification number: H01L23/528 , H01L29/42392 , H01L21/76895 , H01L23/535 , H01L29/456 , H01L29/78696
Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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Patent Agency Ranking
公开(公告)号：US20230275155A1
公开(公告)日：2023-08-31
申请号：US18312673
申请日：2023-05-05
Inventor： Li-Zhen Yu , Chia-Hao Chang , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC: H01L29/78 , H01L29/417 , H01L29/423 , H01L29/66 , H01L23/522 , H01L23/528 , H01L29/49
CPC classification number: H01L29/785 , H01L29/41791 , H01L29/42372 , H01L29/66795 , H01L23/5226 , H01L23/528 , H01L29/4975 , H01L2029/7858
Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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公开(公告)号：US10109582B2
公开(公告)日：2018-10-23
申请号：US15455623
申请日：2017-03-10
Inventor： Chih-Liang Chen , Cheng-Chi Chuang , Chih-Ming Lai , Chia-Tien Wu , Charles Chew-Yuen Young , Hui-Ting Yang , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Shun Li Chen , Shih-Wei Peng , Tien-Lu Lin
IPC: H01L23/528 , H01L21/768 , H01L23/522 , H01L27/02 , H01L29/49
Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
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公开(公告)号：US20180151432A1
公开(公告)日：2018-05-31
申请号：US15611896
申请日：2017-06-02
Inventor： Chih-Liang Chen , Cheng-Chi Chuang , Chih-Ming Lai , Chia-Tien Wu , Charles Chew-Yuen Young , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Wei-Cheng Lin , Lei-Chun Chou
IPC: H01L21/768 , H01L21/311 , H01L23/532 , H01L23/522 , H01L23/528
CPC classification number: H01L21/76897 , H01L21/02126 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/02178 , H01L21/31111 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L21/76877 , H01L21/76883 , H01L21/76885 , H01L23/5226 , H01L23/528 , H01L23/53209 , H01L23/53228 , H01L23/53257 , H01L23/53295
Abstract: A self aligned via and a method for fabricated a semiconductor device using a double-trench constrained self alignment process to form the via. The method includes forming a first trench and depositing a first metal into the first trench. Afterwards, the process includes depositing a dielectric layer over the first metal such that a top surface of the dielectric layer is at substantially the same level as the top surface of the first trench. Next, a second trench is formed and a via is formed by etching the portion of the dielectric layer exposed by the overlapping region between the first trench and the second trench. The via exposes a portion of the first metal and a second metal is deposited into the second trench such that the second metal is electrically coupled to the first metal.
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公开(公告)号：US20220181250A1
公开(公告)日：2022-06-09
申请号：US17676300
申请日：2022-02-21
Inventor： Li-Zhen YU , Chia-Hao Chang , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC: H01L23/528 , H01L29/423 , H01L21/768 , H01L23/535 , H01L29/45 , H01L29/786
Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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公开(公告)号：US20210066182A1
公开(公告)日：2021-03-04
申请号：US17098717
申请日：2020-11-16
Inventor： Chih-Liang Chen , Cheng-Chi Chuang , Chih-Ming Lai , Chia-Tien Wu , Charles Chew-Yuen Young , Hui-Ting Yang , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Shun Li Chen , Shih-Wei Peng , Tien-Lu Lin
IPC: H01L23/528 , H01L21/768 , H01L23/522 , H01L27/02 , H01L29/49
Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
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