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公开(公告)号：US11682730B2
公开(公告)日：2023-06-20
申请号：US16910125
申请日：2020-06-24
Inventor： Li-Zhen Yu , Chia-Hao Chang , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC: H01L29/78 , H01L29/417 , H01L29/423 , H01L29/66 , H01L23/522 , H01L23/528 , H01L29/49
CPC classification number: H01L29/785 , H01L23/528 , H01L23/5226 , H01L29/41791 , H01L29/42372 , H01L29/4975 , H01L29/66795 , H01L2029/7858
Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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公开(公告)号：US11257758B2
公开(公告)日：2022-02-22
申请号：US16910453
申请日：2020-06-24
Inventor： Li-Zhen Yu , Chia-Hao Chang , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC: H01L21/00 , H01L23/528 , H01L29/423 , H01L21/768 , H01L23/535 , H01L29/45 , H01L29/786
Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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公开(公告)号：US20220181250A1
公开(公告)日：2022-06-09
申请号：US17676300
申请日：2022-02-21
Inventor： Li-Zhen YU , Chia-Hao Chang , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC: H01L23/528 , H01L29/423 , H01L21/768 , H01L23/535 , H01L29/45 , H01L29/786
Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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公开(公告)号：US20230326851A1
公开(公告)日：2023-10-12
申请号：US18335175
申请日：2023-06-15
Inventor： Li-Zhen Yu , Chia-Hao Chang , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC: H01L23/528 , H01L29/423 , H01L21/768 , H01L23/535 , H01L29/45 , H01L29/786
CPC classification number: H01L23/528 , H01L29/42392 , H01L21/76895 , H01L23/535 , H01L29/456 , H01L29/78696
Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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Patent Agency Ranking
公开(公告)号：US20230275155A1
公开(公告)日：2023-08-31
申请号：US18312673
申请日：2023-05-05
Inventor： Li-Zhen Yu , Chia-Hao Chang , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC: H01L29/78 , H01L29/417 , H01L29/423 , H01L29/66 , H01L23/522 , H01L23/528 , H01L29/49
CPC classification number: H01L29/785 , H01L29/41791 , H01L29/42372 , H01L29/66795 , H01L23/5226 , H01L23/528 , H01L29/4975 , H01L2029/7858
Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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公开(公告)号：US20250014993A1
公开(公告)日：2025-01-09
申请号：US18885792
申请日：2024-09-16
Inventor： Li-Zhen Yu , Chia-Hao Chang , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao WANG
IPC: H01L23/528 , H01L21/768 , H01L23/535 , H01L29/423 , H01L29/45 , H01L29/786
Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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公开(公告)号：US12100656B2
公开(公告)日：2024-09-24
申请号：US18335175
申请日：2023-06-15
Inventor： Li-Zhen Yu , Chia-Hao Chang , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC: H01L21/00 , H01L21/768 , H01L23/528 , H01L23/535 , H01L29/423 , H01L29/45 , H01L29/786
CPC classification number: H01L23/528 , H01L21/76895 , H01L23/535 , H01L29/42392 , H01L29/456 , H01L29/78696
Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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公开(公告)号：US20230275154A1
公开(公告)日：2023-08-31
申请号：US18312666
申请日：2023-05-05
Inventor： Li-Zhen Yu , Chia-Hao Chang , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC: H01L29/78 , H01L29/417 , H01L29/423 , H01L29/66 , H01L23/522 , H01L23/528 , H01L29/49
CPC classification number: H01L29/785 , H01L29/41791 , H01L29/42372 , H01L29/66795 , H01L23/5226 , H01L23/528 , H01L29/4975 , H01L2029/7858
Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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公开(公告)号：US11721623B2
公开(公告)日：2023-08-08
申请号：US17676300
申请日：2022-02-21
Inventor： Li-Zhen Yu , Chia-Hao Chang , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC: H01L21/00 , H01L23/528 , H01L29/423 , H01L21/768 , H01L23/535 , H01L29/45 , H01L29/786
CPC classification number: H01L23/528 , H01L21/76895 , H01L23/535 , H01L29/42392 , H01L29/456 , H01L29/78696
Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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