公开(公告)号：US11538754B2

公开(公告)日：2022-12-27

申请号：US17233714

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Shih-Wei Peng ,  Wei-Cheng Lin ,  Chih-Ming Lai ,  Jiann-Tyng Tzeng

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/48

Abstract: Methods and devices are described herein for random cut patterning. A first metal line and a second metal line are formed within a cell of a substrate and extend in a vertical direction. A third metal line and a fourth metal line are formed within the cell and are perpendicular to the first metal line and the second metal line, respectively. A first circular region at one end of the first metal line is formed using a first patterning technique and a second circular region at one end of the second metal line is formed using a second patterning technique. The first circular region is laterally extended using a second patterning technique to form the third metal line and the second circular region is laterally extended using the second patterning technique to form the fourth metal line.

公开(公告)号：US20180308796A1

公开(公告)日：2018-10-25

申请号：US15691936

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Shih-Wei Peng ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin

IPC: H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L23/53271

Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The second supply metal tract is wider than the first supply metal tract. The first supply metal tract has a thickness substantially same as the first pattern metal layer. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

公开(公告)号：US20180151432A1

公开(公告)日：2018-05-31

申请号：US15611896

申请日：2017-06-02

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Chih-Liang Chen ,  Cheng-Chi Chuang ,  Chih-Ming Lai ,  Chia-Tien Wu ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Wei-Cheng Lin ,  Lei-Chun Chou

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/31111 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295

Abstract: A self aligned via and a method for fabricated a semiconductor device using a double-trench constrained self alignment process to form the via. The method includes forming a first trench and depositing a first metal into the first trench. Afterwards, the process includes depositing a dielectric layer over the first metal such that a top surface of the dielectric layer is at substantially the same level as the top surface of the first trench. Next, a second trench is formed and a via is formed by etching the portion of the dielectric layer exposed by the overlapping region between the first trench and the second trench. The via exposes a portion of the first metal and a second metal is deposited into the second trench such that the second metal is electrically coupled to the first metal.

公开(公告)号：US20220358275A1

公开(公告)日：2022-11-10

申请号：US17872859

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Wei-An Lai ,  Wei-Cheng Lin ,  Yan-Hao Chen ,  Jiann-Tyng Tzeng ,  Lipen Yuan ,  Hui-Zhong Zhuang ,  Yu-Xuan Huang

IPC: G06F30/392

Abstract: One aspect of this description relates to a method for operating an integrated circuit (IC) manufacturing system. The method includes placing a first nano-sheet structure within a IC layout diagram. The first nano-sheet structure has a first width. The method includes abutting a second nano-sheet structure with the first nano-sheet structure. The second nano-sheet structure has a second width. The second width is less than the first width. The method includes generating and storing the IC layout diagram in a storage device.

公开(公告)号：US11133255B2

公开(公告)日：2021-09-28

申请号：US16852604

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Shih-Wei Peng ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin

IPC: H01L23/528 ,  H01L23/532

Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

公开(公告)号：US10950456B2

公开(公告)日：2021-03-16

申请号：US16600630

申请日：2019-10-14

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Lei-Chun Chou ,  Chih-Liang Chen ,  Chih-Ming Lai ,  Charles Chew-Yuen Young ,  Chin-Yuan Tseng ,  Hsin-Chih Chen ,  Shi Ning Ju ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Wei-Cheng Lin ,  Wei-Liang Lin

IPC: H01L21/308 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.

公开(公告)号：US20200243447A1

公开(公告)日：2020-07-30

申请号：US16852604

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Shih-Wei Peng ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin

IPC: H01L23/528 ,  H01L23/532

Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

公开(公告)号：US20200058681A1

公开(公告)日：2020-02-20

申请号：US16102803

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Wei-An Lai ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin ,  Lipen Yuan ,  Yan-Hao Chen

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.

公开(公告)号：US12299372B2

公开(公告)日：2025-05-13

申请号：US18361948

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Shih-Wei Peng ,  Lipen Yuan ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin

IPC: G06F30/392 ,  G06F30/398 ,  G06F119/06

Abstract: An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.

公开(公告)号：US20220292244A1

公开(公告)日：2022-09-15

申请号：US17199551

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Wei-An Lai ,  Wei-Cheng Lin ,  Yan-Hao Chen ,  Jiann-Tyng Tzeng ,  Lipen Yuan ,  Hui-Zhong Zhuang ,  Yu-Xuan Huang

IPC: G06F30/392

Abstract: One aspect of this description relates to a method for operating an integrated circuit (IC) manufacturing system. The method includes placing a first nano-sheet structure within a IC layout diagram. The first nano-sheet structure has a first width. The method includes abutting a second nano-sheet structure with the first nano-sheet structure. The second nano-sheet structure has a second width. The second width is less than the first width. The method includes generating and storing the IC layout diagram in a storage device.