公开(公告)号：US09406778B2

公开(公告)日：2016-08-02

申请号：US14461502

申请日：2014-08-18

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Guan-Lin Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a doped region, in some embodiments. The semiconductor device includes a gate over a channel portion of the fin. The gate including a gate electrode over a gate dielectric between a first sidewall spacer and a second sidewall spacer. The first sidewall spacer includes an initial first sidewall spacer over a first portion of a dielectric material. The second sidewall spacer includes an initial second sidewall spacer over a second portion of the dielectric material.

Abstract translation: 本文提供半导体器件和形成方法。 在一些实施例中，半导体器件包括具有掺杂区域的鳍。 半导体器件包括在鳍的通道部分上的栅极。 栅极包括在第一侧壁间隔物和第二侧壁间隔物之间​​的栅电介质上的栅电极。 第一侧壁间隔物包括介电材料的第一部分上的初始第一侧壁间隔物。 第二侧壁间隔物包括在电介质材料的第二部分上的初始第二侧壁间隔物。

公开(公告)号：US10115788B2

公开(公告)日：2018-10-30

申请号：US14512963

申请日：2014-10-13

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Guan-Lin Chen

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/267 ,  H01L29/10 ,  H01L29/167 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device having a horizontal gate all around structure is provided. The semiconductor device includes a substrate and a fin. The fin is disposed on the substrate, and includes an anti-punch through (APT) layer formed of a material at a dose of about 1E18 atoms/cm2 to about 1E19 atoms/cm2, and a barrier layer formed above the APT layer. A method of forming a semiconductor device having a horizontal gate all around structure is also provided.

公开(公告)号：US20150236114A1

公开(公告)日：2015-08-20

申请号：US14181800

申请日：2014-02-17

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Guan-Lin Chen ,  Chao-Hsiung Wang ,  Chi-Wen Liu

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a barrier including carbon over a fin, the fin including a doped region. The semiconductor device includes an epitaxial (Epi) cap over the barrier, the Epi cap including phosphorus. The barrier inhibits phosphorus diffusion from the Epi cap into the fin as compared to a device that lacks such a barrier. The inhibition of the phosphorus diffusion reduces a short channel effect, thus improving the semiconductor device function.

Abstract translation: 本文提供半导体器件和形成方法。 半导体器件包括在鳍上方包括碳的势垒，所述鳍包括掺杂区。 半导体器件包括在屏障上的外延（Epi）帽，Epi帽包括磷。 与不具有这种屏障的装置相比，阻挡层阻止磷从Epi帽扩散到鳍中。 磷扩散的抑制减小了沟道效应，从而提高了半导体器件的功能。

公开(公告)号：US11296081B2

公开(公告)日：2022-04-05

申请号：US16910488

申请日：2020-06-24

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Shi Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Kuan-Lun Cheng ,  Guan-Lin Chen

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66

Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.

公开(公告)号：US12191305B2

公开(公告)日：2025-01-07

申请号：US18360889

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Shi Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Kuan-Lun Cheng ,  Guan-Lin Chen

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.

公开(公告)号：US11798944B2

公开(公告)日：2023-10-24

申请号：US17712255

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Shi Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Kuan-Lun Cheng ,  Guan-Lin Chen

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.

公开(公告)号：US09627264B2

公开(公告)日：2017-04-18

申请号：US15214826

申请日：2016-07-20

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Guan-Lin Chen

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a doped region, in some embodiments. The semiconductor device includes a gate over a channel portion of the fin. The gate including a gate electrode over a gate dielectric between a first sidewall spacer and a second sidewall spacer. The first sidewall spacer includes an initial first sidewall spacer over a first portion of a dielectric material. The second sidewall spacer includes an initial second sidewall spacer over a second portion of the dielectric material.

公开(公告)号：US20160329250A1

公开(公告)日：2016-11-10

申请号：US15214826

申请日：2016-07-20

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Guan-Lin Chen

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a doped region, in some embodiments. The semiconductor device includes a gate over a channel portion of the fin. The gate including a gate electrode over a gate dielectric between a first sidewall spacer and a second sidewall spacer. The first sidewall spacer includes an initial first sidewall spacer over a first portion of a dielectric material. The second sidewall spacer includes an initial second sidewall spacer over a second portion of the dielectric material.

公开(公告)号：US09870949B2

公开(公告)日：2018-01-16

申请号：US15485270

申请日：2017-04-12

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Guan-Lin Chen

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFet, as compared to a FinFet including fins that do not include a dielectric disposed within a furrow.

公开(公告)号：US09837537B2

公开(公告)日：2017-12-05

申请号：US14181800

申请日：2014-02-17

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Guan-Lin Chen ,  Chao-Hsiung Wang ,  Chi-Wen Liu

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a barrier including carbon over a fin, the fin including a doped region. The semiconductor device includes an epitaxial (Epi) cap over the barrier, the Epi cap including phosphorus. The barrier inhibits phosphorus diffusion from the Epi cap into the fin as compared to a device that lacks such a barrier. The inhibition of the phosphorus diffusion reduces a short channel effect, thus improving the semiconductor device function.