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公开(公告)号：US20240290652A1
公开(公告)日：2024-08-29
申请号：US18657752
申请日：2024-05-07
IPC分类号： H01L21/768 , H01L21/324 , H01L29/08 , H01L29/165 , H01L29/45 , H01L29/66 , H01L29/78
CPC分类号： H01L21/76814 , H01L21/324 , H01L21/76805 , H01L21/76843 , H01L21/76895 , H01L29/0847 , H01L29/165 , H01L29/45 , H01L29/7833 , H01L29/7848 , H01L29/665 , H01L29/6656
摘要： A semiconductor device includes a first gate stack structure over a substrate, a source/drain epitaxial layer, a lightly doped region, and a silicide region. The source/drain epitaxial layer is disposed in the substrate and adjacent to the first gate stack structure. The lightly doped region is located in the substrate to be electrically connected to the source/drain epitaxial layer. The lightly doped region includes a first portion protrudes from a sidewall of the source/drain epitaxial layer. The silicide region is in contact with a top surface and sidewalls of a top portion of the source/drain epitaxial layer and a top surface of the first portion of the lightly doped region. The top portion of the source/drain epitaxial layer is higher than the top surface of the first portion of the lightly doped region.
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公开(公告)号：US12027433B2
公开(公告)日：2024-07-02
申请号：US17885401
申请日：2022-08-10
CPC分类号： H01L23/04 , H01L21/52 , H01L23/06 , H01L23/14 , H01L23/49816 , H01L24/14 , H01L2021/60022
摘要： A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.
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公开(公告)号：US11990474B2
公开(公告)日：2024-05-21
申请号：US18151990
申请日：2023-01-09
IPC分类号： H01L27/088 , H01L21/8238 , H01L27/02 , H01L27/092 , H01L29/10 , H01L29/78 , H03K3/03
CPC分类号： H01L27/0886 , H01L21/823807 , H01L21/823821 , H01L21/823871 , H01L21/823878 , H01L27/0207 , H01L27/092 , H01L27/0924 , H01L29/1041 , H01L29/7835 , H01L29/785 , H01L21/823814 , H03K3/0315
摘要： A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.
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公开(公告)号：US11552076B2
公开(公告)日：2023-01-10
申请号：US16938528
申请日：2020-07-24
IPC分类号： H01L27/088 , H01L27/02 , H01L27/092 , H01L29/10 , H01L29/78 , H01L21/8238 , H03K3/03
摘要： A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.
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公开(公告)号：US10937858B2
公开(公告)日：2021-03-02
申请号：US16852749
申请日：2020-04-20
摘要： A method of manufacturing a semiconductor structure is provided. The method includes: providing a substrate including an electrical component; forming a capacitor structure in the substrate, proximal to a heterogeneous interface of the substrate, and physically and electrically isolated from the electrical component; forming a conductive terminal over and electrically connected with the capacitor structure; and contacting the conductive terminal with a probe to measure an electrical parameter of the capacitor structure, wherein the electrical parameter corresponds to a humidity permeability at the heterogeneous interface. A semiconductor structure thereof is also provided.
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公开(公告)号：US10535686B2
公开(公告)日：2020-01-14
申请号：US15954305
申请日：2018-04-16
发明人： Victor Chiang Liang , Fu-Huan Tsai , Fang-Ting Kuo , Meng-Chang Ho , Yu-Lin Wei , Chi-Feng Huang
IPC分类号： H01L27/108 , H01L27/146 , H01L29/66 , H01L27/07 , H01L29/93
摘要： A semiconductor device includes a substrate, wherein the substrate includes a channel region. The semiconductor device further includes an isolation feature in the substrate. The isolation feature includes a first portion in the substrate, and a second portion extending along a top surface of the substrate. The second portion partially covers the channel region. The semiconductor device further includes a gate structure over the substrate, wherein the gate structure partially covers the second portion of the isolation feature.
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公开(公告)号：US10134868B2
公开(公告)日：2018-11-20
申请号：US15942663
申请日：2018-04-02
IPC分类号： H01L21/283 , H01L29/66 , H01L21/768 , H01L29/78 , H01L21/285
摘要： A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.
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公开(公告)号：US20180226488A1
公开(公告)日：2018-08-09
申请号：US15942663
申请日：2018-04-02
IPC分类号： H01L29/66 , H01L29/78 , H01L21/768 , H01L21/285
CPC分类号： H01L29/66492 , H01L21/28518 , H01L21/76897 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.
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公开(公告)号：US09947762B2
公开(公告)日：2018-04-17
申请号：US14861802
申请日：2015-09-22
CPC分类号： H01L29/66492 , H01L21/28518 , H01L21/76897 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.
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公开(公告)号：US09337269B2
公开(公告)日：2016-05-10
申请号：US14178053
申请日：2014-02-11
CPC分类号： H01L29/1041 , H01L29/66795 , H01L29/785
摘要： A fin field effect transistor (FinFET), and a method of fabrication, is introduced. In an embodiment, trenches are formed in a substrate, wherein a region between adjacent trenches defines a fin. A dielectric material is formed in the trenches. The fins are doped to form source, drain and buried channel regions. A gate stack is formed over the buried channel regions. Contacts are formed to provide electrical contacts to the source/drain regions and the gate.
摘要翻译： 引入了鳍状场效应晶体管（FinFET）和制造方法。 在一个实施例中，沟槽形成在衬底中，其中相邻沟槽之间的区域限定鳍。 在沟槽中形成电介质材料。 鳍片被掺杂以形成源极，漏极和掩埋沟道区域。 栅极堆叠形成在掩埋沟道区域上。 形成触点以提供到源极/漏极区域和栅极的电接触。
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