公开(公告)号：US20240365532A1

公开(公告)日：2024-10-31

申请号：US18507204

申请日：2023-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Jin Park ,  Jun Soo Kim ,  Ji Ho Park ,  Ki Seok Lee ,  Myeong-Dong Lee ,  Ho Sang Lee

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

Abstract: Semiconductor memory devices including capacitors and methods for manufacturing thereof. The semiconductor memory device may include a substrate, an element isolation pattern defining an active area in the substrate, a first conductive pattern on the substrate and the element isolation pattern, and extending in a first direction, wherein the first conductive pattern is connected to a first portion of the active area, a capacitor structure on the substrate and the element isolation pattern and connected to a second portion of the active area, a gate trench defined in the substrate and the element isolation pattern and extending in a second direction, wherein a first trench width of a portion of the gate trench in the active area is greater than a second trench width of a portion of the gate trench in the element isolation pattern.

公开(公告)号：US11468919B2

公开(公告)日：2022-10-11

申请号：US16841850

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin Park ,  Won Seok Yoo ,  Keun Nam Kim ,  Hyo-Sub Kim ,  So Hyun Park ,  In Kyoung Heo ,  Yoo Sang Hwang

IPC: G11C5/06 ,  H01L27/108

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate a bit line structure disposed on the substrate, a trench adjacent to at least one side of the bit line structure, a storage contact structure disposed within the trench, and comprising a storage contact, a silicide layer, and a storage pad which are stacked sequentially. A spacer structure is disposed between the bit line structure and the storage contact structure.

公开(公告)号：US10811541B2

公开(公告)日：2020-10-20

申请号：US16254842

申请日：2019-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum Kim ,  Hyoung Sub Kim ,  Seong Heum Choi ,  Jin Yong Kim ,  Tae Jin Park ,  Seung Hun Lee

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/30

Abstract: A semiconductor device includes a gate electrode extending in a first direction on a substrate, a first active pattern extending in a second direction intersecting the first direction on the substrate to penetrate the gate electrode, the first active pattern including germanium, an epitaxial pattern on a side wall of the gate electrode, a first semiconductor oxide layer between the first active pattern and the gate electrode, and including a first semiconductor material, and a second semiconductor oxide layer between the gate electrode and the epitaxial pattern, and including a second semiconductor material. A concentration of germanium of the first semiconductor material may be less than a concentration of germanium of the first active pattern, and the concentration of germanium of the first semiconductor material may be different from a concentration of germanium of the second semiconductor material.

公开(公告)号：US10559752B2

公开(公告)日：2020-02-11

申请号：US15678583

申请日：2017-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il Mok Park ,  Tae Jin Park

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor device includes a first word line and a first bit line. The semiconductor device further includes a mold film disposed between the first word line and the first bit line, and a first memory cell disposed in the mold film. The first memory cell includes a first lower electrode in contact with the first word line. Side surfaces of the first lower electrode are in direct contact with the mold film. The first memory cell includes a first phase-change memory in contact with the first lower electrode, a first intermediate electrode in contact with the first phase-change memory, a first ovonic threshold switch (OTS) in contact with the first intermediate electrode, and a first upper electrode disposed between the first OTS and the first bit line, the first upper electrode in contact with the first OTS and the first bit line.

公开(公告)号：US10084049B2

公开(公告)日：2018-09-25

申请号：US15685255

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum Kim ,  Gyeom Kim ,  Seok Hoon Kim ,  Tae Jin Park ,  Jeong Ho Yoo ,  Cho Eun Lee ,  Hyun Jung Lee ,  Sun Jung Kim ,  Dong Suk Shin

IPC: H01L27/12 ,  H01L29/417 ,  H01L27/092 ,  H01L29/51 ,  H01L29/423 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L29/41725 ,  H01L21/02425 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/485 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2924/0002

Abstract: A semiconductor device includes: a substrate having an active region; a gate structure disposed in the active region; source/drain regions respectively formed within portions of the active region disposed on both sides of the gate structure; a metal silicide layer disposed on a surface of each of the source/drain regions; and contact plugs disposed on the source/drain regions and electrically connected to the source/drain regions through the metal silicide layer, respectively. The metal silicide layer is formed so as to have a monocrystalline structure.

公开(公告)号：US11705503B2

公开(公告)日：2023-07-18

申请号：US17038004

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Jin Bum Kim ,  MunHyeon Kim ,  Hyoung Sub Kim ,  Tae Jin Park ,  Kwan Heum Lee ,  Chang Woo Noh ,  Maria Toledano Lu Que ,  Hong Bae Park ,  Si Hyung Lee ,  Sung Man Whang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66439 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

公开(公告)号：US10211322B1

公开(公告)日：2019-02-19

申请号：US15896277

申请日：2018-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum Kim ,  Tae Jin Park ,  Jong Min Lee ,  Seok Hoon Kim ,  Dong Chan Suh ,  Jeong Ho Yoo ,  Ha Kyu Seong ,  Dong Suk Shin

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a channel pattern on a substrate, the channel pattern extending in a first direction; a gate pattern on the substrate, the gate pattern extending in a second direction crossing the first direction and surrounding the channel pattern; and an interface layer between the channel pattern and the gate pattern, the interface layer being formed on at least one surface of an upper surface and a lower surface of the channel pattern.