公开(公告)号：US20240355362A1

公开(公告)日：2024-10-24

申请号：US18503222

申请日：2023-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Seong Shin ,  Ki Seok Lee ,  Keun Nam Kim ,  Hui-Jung Kim ,  Chan-Sic Yoon

IPC: G11C5/06 ,  H10B12/00

CPC classification number: G11C5/063 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor memory device includes a substrate comprising an element isolation layer, a bit line that extends on the substrate in a first direction, a cell buffer insulating layer between the bit line and the substrate and comprising an upper cell buffer insulating layer and a lower cell buffer insulating layer, a lower storage contact disposed on a plurality of sides of the bit line and comprising a semiconductor epitaxial pattern, a storage pad on the lower storage contact and connected to the lower storage contact and an information storage unit on the storage pad and connected to the storage pad, wherein the upper cell buffer insulating layer is between the lower cell buffer insulating layer and the bit line, and each of the lower cell buffer insulating layer and the upper cell buffer insulating layer comprises an upper surface and a lower surface that are opposite to each other.

公开(公告)号：US10679997B2

公开(公告)日：2020-06-09

申请号：US16391888

申请日：2019-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook Jung ,  Dong Oh Kim ,  Seok Han Park ,  Chan Sic Yoon ,  Ki Seok Lee ,  Ho In Lee ,  Ju Yeon Jang ,  Je Min Park ,  Jin Woo Hong

IPC: H01L27/108 ,  H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/10 ,  H01L23/535

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US10573652B2

公开(公告)日：2020-02-25

申请号：US15945401

申请日：2018-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-Dong Lee ,  Jun-Won Lee ,  Ki Seok Lee ,  Bong-Soo Kim ,  Seok Han Park ,  Sung Hee Han ,  Yoo Sang Hwang

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.

公开(公告)号：US10522550B2

公开(公告)日：2019-12-31

申请号：US16183826

申请日：2018-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Seok Lee ,  Jeong Seop Shim ,  Mi Na Lee ,  Augustin Jinwoo Hong ,  Je Min Park ,  Hye Jin Seong ,  Seung Min Oh ,  Do Yeong Lee ,  Ji Seung Lee ,  Jin Seong Lee

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.

公开(公告)号：US10325802B2

公开(公告)日：2019-06-18

申请号：US15712410

申请日：2017-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho In Lee ,  Dong Oh Kim ,  Seok Han Park ,  Chan Sic Yoon ,  Ki Wook Jung ,  Jinwoo Augustin Hong ,  Je Min Park ,  Ki Seok Lee ,  Ju Yeon Jang

IPC: H01L21/762 ,  H01L27/108 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L29/43 ,  H01L29/06

Abstract: A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and second sealing films, such that an etch selectivity of the second sealing film is smaller than that of the first sealing film, patterning the first and second sealing films to expose the second region and a portion of the device isolation film, such that an undercut is defined under a lower surface of the second sealing film, forming a filling film filling the undercut, a thickness of the filling film being thicker on a side surface of the second sealing film than on an upper surface thereof, removing a portion of the filling film to form a filling spacer in the undercut, forming a high-k dielectric film and a metal film on the filling spacer, and patterning the high-k dielectric film and the metal film.

公开(公告)号：US20240119978A1

公开(公告)日：2024-04-11

申请号：US18329067

申请日：2023-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Woo Han ,  Hyun Geun Choi ,  Ki Seok Lee ,  Seok Han Park

IPC: G11C7/18 ,  G11C5/06 ,  G11C7/12

CPC classification number: G11C7/18 ,  G11C5/063 ,  G11C7/12

Abstract: Provided a semiconductor memory device. The semiconductor memory device includes a substrate, a gate electrode on the substrate, a bit line on the substrate, a cell semiconductor pattern on a side of the gate electrode and electrically connected to the bit line, a capacitor structure including a first electrode electrically connected to the cell semiconductor pattern, a second electrode on the first electrode, and a capacitor dielectric film between the first electrode and the second electrode, a bit line strapping line spaced apart from the bit line in the second direction, and electrically connected to the bit line, a bit line selection line between the bit line and the bit line strapping line, and a selection semiconductor pattern between the bit line and the bit line strapping line and electrically connected to all of the bit line, the bit line strapping line, and the bit line selection line.

公开(公告)号：US20200295013A1

公开(公告)日：2020-09-17

申请号：US16890456

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook Jung ,  Dong Oh Kim ,  Seok Han Park ,  Chan Sic Yoon ,  Ki Seok Lee ,  Ho In Lee ,  Ju Yeon Jang ,  Je Min Park ,  Jin Woo Hong

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/108 ,  H01L29/10 ,  H01L21/8238 ,  H01L23/535

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US09916979B2

公开(公告)日：2018-03-13

申请号：US15381135

申请日：2016-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan Sic Yoon ,  Ki Seok Lee ,  Dong Oh Kim ,  Yong Jae Kim

IPC: H01L21/02 ,  H01L21/027 ,  G03F1/38

CPC classification number: H01L21/027 ,  G03F1/38 ,  H01L21/02107 ,  H01L21/02697 ,  H01L27/0207 ,  H01L27/10888

Abstract: Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, forming a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.

公开(公告)号：US11696436B2

公开(公告)日：2023-07-04

申请号：US17035082

申请日：2020-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Seok Lee ,  Jae Hyun Yoon ,  Kyu Jin Kim ,  Keun Nam Kim ,  Hui-Jung Kim ,  Kyu Hyun Lee ,  Sang-Il Han ,  Sung Hee Han ,  Yoo Sang Hwang

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053

Abstract: A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part.

公开(公告)号：US11594538B2

公开(公告)日：2023-02-28

申请号：US17469340

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Ho Lee ,  Eun A Kim ,  Ki Seok Lee ,  Jay-Bok Choi ,  Keun Nam Kim ,  Yong Seok Ahn ,  Jin-Hwan Chun ,  Sang Yeon Han ,  Sung Hee Han ,  Seung Uk Han ,  Yoo Sang Hwang

IPC: H01L21/00 ,  H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.