公开(公告)号：US20230180455A1

公开(公告)日：2023-06-08

申请号：US17933875

申请日：2022-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Geun Choi ,  Ki Seok Lee

IPC: H01L27/108

CPC classification number: H01L27/10805

Abstract: According to some embodiments of the present inventive concept, a semiconductor memory device includes a plurality of mold insulating layers on a substrate and spaced apart from one another, a plurality of semiconductor patterns which are between respective ones of the plurality of mold insulating layers adjacent to each other, a plurality of gate electrodes, on respective ones of the plurality of semiconductor patterns, an information storage element which includes a first electrode electrically connected to each of the plurality of semiconductor patterns, a second electrode on the first electrode, and a capacitor dielectric film between the first electrode and the second electrode, a bit line on the substrate and contacts the semiconductor pattern, and an insulating buffer film between the first electrodes and the second electrode and on a sidewall of a respective one of the plurality of mold insulating layers.

公开(公告)号：US20240119978A1

公开(公告)日：2024-04-11

申请号：US18329067

申请日：2023-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Woo Han ,  Hyun Geun Choi ,  Ki Seok Lee ,  Seok Han Park

IPC: G11C7/18 ,  G11C5/06 ,  G11C7/12

CPC classification number: G11C7/18 ,  G11C5/063 ,  G11C7/12

Abstract: Provided a semiconductor memory device. The semiconductor memory device includes a substrate, a gate electrode on the substrate, a bit line on the substrate, a cell semiconductor pattern on a side of the gate electrode and electrically connected to the bit line, a capacitor structure including a first electrode electrically connected to the cell semiconductor pattern, a second electrode on the first electrode, and a capacitor dielectric film between the first electrode and the second electrode, a bit line strapping line spaced apart from the bit line in the second direction, and electrically connected to the bit line, a bit line selection line between the bit line and the bit line strapping line, and a selection semiconductor pattern between the bit line and the bit line strapping line and electrically connected to all of the bit line, the bit line strapping line, and the bit line selection line.