公开(公告)号：US20240355362A1

公开(公告)日：2024-10-24

申请号：US18503222

申请日：2023-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Seong Shin ,  Ki Seok Lee ,  Keun Nam Kim ,  Hui-Jung Kim ,  Chan-Sic Yoon

IPC: G11C5/06 ,  H10B12/00

CPC classification number: G11C5/063 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor memory device includes a substrate comprising an element isolation layer, a bit line that extends on the substrate in a first direction, a cell buffer insulating layer between the bit line and the substrate and comprising an upper cell buffer insulating layer and a lower cell buffer insulating layer, a lower storage contact disposed on a plurality of sides of the bit line and comprising a semiconductor epitaxial pattern, a storage pad on the lower storage contact and connected to the lower storage contact and an information storage unit on the storage pad and connected to the storage pad, wherein the upper cell buffer insulating layer is between the lower cell buffer insulating layer and the bit line, and each of the lower cell buffer insulating layer and the upper cell buffer insulating layer comprises an upper surface and a lower surface that are opposite to each other.