公开(公告)号：US11676816B2

公开(公告)日：2023-06-13

申请号：US16530286

申请日：2019-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min Park ,  Se Myeong Jang ,  Bong Soo Kim ,  Je Min Park

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/762

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L21/76224

Abstract: A method of forming a semiconductor device includes forming first sacrificial patterns on a lower structure, forming first remaining mask layers having a “U” shape between the first sacrificial patterns to be in contact with the first sacrificial patterns, forming first remaining mask patterns by pattering the first remaining mask layers, each of the first remaining mask patterns including a horizontal portion, parallel to an upper surface of the lower structure, and a vertical portion, perpendicular to the upper surface of the lower structure, forming second mask patterns spaced apart from the vertical portions of the first remaining mask patterns, removing the first sacrificial patterns remaining after forming the second mask patterns, and forming first mask patterns by etching the horizontal portions of the first remaining mask patterns.

公开(公告)号：US20240114675A1

公开(公告)日：2024-04-04

申请号：US18541566

申请日：2023-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Han ,  Je Min Park

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/34

Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

公开(公告)号：US20200295013A1

公开(公告)日：2020-09-17

申请号：US16890456

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook Jung ,  Dong Oh Kim ,  Seok Han Park ,  Chan Sic Yoon ,  Ki Seok Lee ,  Ho In Lee ,  Ju Yeon Jang ,  Je Min Park ,  Jin Woo Hong

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/108 ,  H01L29/10 ,  H01L21/8238 ,  H01L23/535

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US11882688B2

公开(公告)日：2024-01-23

申请号：US17403984

申请日：2021-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Han ,  Je Min Park

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/34

Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

公开(公告)号：US20220189962A1

公开(公告)日：2022-06-16

申请号：US17403984

申请日：2021-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Han ,  Je Min Park

IPC: H01L27/108

Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

公开(公告)号：US20200152462A1

公开(公告)日：2020-05-14

申请号：US16530286

申请日：2019-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min Park ,  Se Myeong Jang ,  Bong Soo Kim ,  Je Min Park

IPC: H01L21/033 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3213

Abstract: A method of forming a semiconductor device includes forming first sacrificial patterns on a lower structure, forming first remaining mask layers having a “U” shape between the first sacrificial patterns to be in contact with the first sacrificial patterns, forming first remaining mask patterns by pattering the first remaining mask layers, each of the first remaining mask patterns including a horizontal portion, parallel to an upper surface of the lower structure, and a vertical portion, perpendicular to the upper surface of the lower structure, forming second mask patterns spaced apart from the vertical portions of the first remaining mask patterns, removing the first sacrificial patterns remaining after forming the second mask patterns, and forming first mask patterns by etching the horizontal portions of the first remaining mask patterns.

公开(公告)号：US10679997B2

公开(公告)日：2020-06-09

申请号：US16391888

申请日：2019-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook Jung ,  Dong Oh Kim ,  Seok Han Park ,  Chan Sic Yoon ,  Ki Seok Lee ,  Ho In Lee ,  Ju Yeon Jang ,  Je Min Park ,  Jin Woo Hong

IPC: H01L27/108 ,  H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/10 ,  H01L23/535

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US10522550B2

公开(公告)日：2019-12-31

申请号：US16183826

申请日：2018-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Seok Lee ,  Jeong Seop Shim ,  Mi Na Lee ,  Augustin Jinwoo Hong ,  Je Min Park ,  Hye Jin Seong ,  Seung Min Oh ,  Do Yeong Lee ,  Ji Seung Lee ,  Jin Seong Lee

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.

公开(公告)号：US10325802B2

公开(公告)日：2019-06-18

申请号：US15712410

申请日：2017-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho In Lee ,  Dong Oh Kim ,  Seok Han Park ,  Chan Sic Yoon ,  Ki Wook Jung ,  Jinwoo Augustin Hong ,  Je Min Park ,  Ki Seok Lee ,  Ju Yeon Jang

IPC: H01L21/762 ,  H01L27/108 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L29/43 ,  H01L29/06

Abstract: A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and second sealing films, such that an etch selectivity of the second sealing film is smaller than that of the first sealing film, patterning the first and second sealing films to expose the second region and a portion of the device isolation film, such that an undercut is defined under a lower surface of the second sealing film, forming a filling film filling the undercut, a thickness of the filling film being thicker on a side surface of the second sealing film than on an upper surface thereof, removing a portion of the filling film to form a filling spacer in the undercut, forming a high-k dielectric film and a metal film on the filling spacer, and patterning the high-k dielectric film and the metal film.

公开(公告)号：US20180166447A1

公开(公告)日：2018-06-14

申请号：US15677726

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Ung Pak ,  Won Chul Lee ,  Je Min Park

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10808 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/87 ,  H01L28/91

Abstract: A semiconductor device includes a substrate, first, second and third structures disposed on the substrate and spaced apart from one another in a first direction, wherein each of the first, second and third structures includes lower electrodes, and a supporter pattern supporting the first, second and third structures and including a first region and a second region, wherein the first region exposes first parts of sidewalls of the first, second and third structures, and the second region surrounds second parts of the sidewalls of the first, second and third structures. A first length of a sidewall of the supporter pattern between the first and second structures is greater than a first distance between the first and second structures. A second length of a sidewall of the supporter pattern between the second and third structures is greater than a second distance between the second and third structures.