公开(公告)号：US20180301456A1

公开(公告)日：2018-10-18

申请号：US15821089

申请日：2017-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Jun Soo Kim ,  Hui Jung Kim ,  Tae Yoon An ,  Satoru Yamada ,  Won Sok Lee ,  Nam Ho Jeon ,  Moon Young Jeong ,  Ki Jae Hur ,  Jae Ho Hong

IPC: H01L27/108 ,  H01L27/12

CPC classification number: H01L27/10802 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/1207 ,  H01L29/4236

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

公开(公告)号：US20130264630A1

公开(公告)日：2013-10-10

申请号：US13785810

申请日：2013-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Soo Kim ,  Dong Jin Lee

IPC: H01L29/792

CPC classification number: H01L29/7926 ,  H01L27/0886 ,  H01L27/10861 ,  H01L27/10876 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7855 ,  H01L29/792

Abstract: Semiconductor devices have transistors capable of adjusting threshold voltages through a body bias effect. The semiconductor devices include transistors having a front gate on a substrate, a back gate between adjacent transistors, and a carrier storage layer configured to surround the back gate and to trap a carrier. A threshold voltage of a transistor may be changed in response to voltage applied to the back gate. Related fabrication methods are also described.

Abstract translation: 半导体器件具有能够通过体偏置效应来调节阈值电压的晶体管。 半导体器件包括在衬底上具有前栅极的晶体管，相邻晶体管之间的背栅极和被配置为围绕背栅极并捕获载流子的载流子存储层。 晶体管的阈值电压可以响应于施加到背栅的电压而改变。 还描述了相关的制造方法。

公开(公告)号：US20180108662A1

公开(公告)日：2018-04-19

申请号：US15835071

申请日：2017-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Hee Cho ,  Woo Song Ahn ,  Min Su Choi ,  Satoru Yamada ,  Jun Soo Kim ,  Sung Sam Lee

IPC: H01L27/108 ,  H01L29/51 ,  H01L29/423 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10876 ,  H01L28/90 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/51

Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.

公开(公告)号：US09024373B2

公开(公告)日：2015-05-05

申请号：US13785810

申请日：2013-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Soo Kim ,  Dong Jin Lee

IPC: H01L29/792 ,  H01L29/66 ,  H01L27/108 ,  H01L49/02 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7926 ,  H01L27/0886 ,  H01L27/10861 ,  H01L27/10876 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7855 ,  H01L29/792

Abstract: Semiconductor devices have transistors capable of adjusting threshold voltages through a body bias effect. The semiconductor devices include transistors having a front gate on a substrate, a back gate between adjacent transistors, and a carrier storage layer configured to surround the back gate and to trap a carrier. A threshold voltage of a transistor may be changed in response to voltage applied to the back gate. Related fabrication methods are also described.

Abstract translation: 半导体器件具有能够通过体偏置效应来调节阈值电压的晶体管。 半导体器件包括在衬底上具有前栅极的晶体管，相邻晶体管之间的背栅极和被配置为围绕背栅极并捕获载流子的载流子存储层。 晶体管的阈值电压可以响应于施加到背栅的电压而改变。 还描述了相关的制造方法。

公开(公告)号：US20240365532A1

公开(公告)日：2024-10-31

申请号：US18507204

申请日：2023-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Jin Park ,  Jun Soo Kim ,  Ji Ho Park ,  Ki Seok Lee ,  Myeong-Dong Lee ,  Ho Sang Lee

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

Abstract: Semiconductor memory devices including capacitors and methods for manufacturing thereof. The semiconductor memory device may include a substrate, an element isolation pattern defining an active area in the substrate, a first conductive pattern on the substrate and the element isolation pattern, and extending in a first direction, wherein the first conductive pattern is connected to a first portion of the active area, a capacitor structure on the substrate and the element isolation pattern and connected to a second portion of the active area, a gate trench defined in the substrate and the element isolation pattern and extending in a second direction, wherein a first trench width of a portion of the gate trench in the active area is greater than a second trench width of a portion of the gate trench in the element isolation pattern.

公开(公告)号：US10770463B2

公开(公告)日：2020-09-08

申请号：US16437784

申请日：2019-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Jun Soo Kim ,  Hui Jung Kim ,  Tae Yoon An ,  Satoru Yamada ,  Won Sok Lee ,  Nam Ho Jeon ,  Moon Young Jeong ,  Ki Jae Hur ,  Jae Ho Hong

IPC: H01L27/108 ,  H01L27/12 ,  H01L21/84 ,  H01L29/423 ,  H01L21/768

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

公开(公告)号：US10361205B2

公开(公告)日：2019-07-23

申请号：US15821089

申请日：2017-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Jun Soo Kim ,  Hui Jung Kim ,  Tae Yoon An ,  Satoru Yamada ,  Won Sok Lee ,  Nam Ho Jeon ,  Moon Young Jeong ,  Ki Jae Hur ,  Jae Ho Hong

IPC: H01L27/108 ,  H01L27/12 ,  H01L21/768 ,  H01L29/423

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

公开(公告)号：US09853031B1

公开(公告)日：2017-12-26

申请号：US15433193

申请日：2017-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Hee Cho ,  Woo Song Ahn ,  Min Su Choi ,  Satoru Yamada ,  Jun Soo Kim ,  Sung Sam Lee

IPC: H01L23/48 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L49/02

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10876 ,  H01L28/90 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/51

Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.

公开(公告)号：US10199379B2

公开(公告)日：2019-02-05

申请号：US15835071

申请日：2017-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Hee Cho ,  Woo Song Ahn ,  Min Su Choi ,  Satoru Yamada ,  Jun Soo Kim ,  Sung Sam Lee

IPC: H01L29/51 ,  H01L27/108 ,  H01L49/02 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.