Method and device for providing content in mobile communication system

    公开(公告)号:US10158698B2

    公开(公告)日:2018-12-18

    申请号:US14433626

    申请日:2013-10-04

    Abstract: A method for transmitting data in a core cache server of a communication system, according to one embodiment of the present invention, comprises the steps of: receiving, from a source base station, a core cache search signal; selecting a relay core cache unit according to the received core cache search signal; and transmitting content data to a target base station through the selected relay core cache unit. A cache server for transmitting and receiving data in a communication system, according to another embodiment of the present invention, comprises: one or more core cache units for storing content data; a receiving unit for receiving, from a source base station, a core cache search signal; a control unit for selecting a relay core cache unit among the one or more core cache units according to the received core cache search signal; and a transmission unit for transmitting the content data to a target base station through the selected relay core cache unit. When the present invention is used, the source base station can continuously provide content to a terminal by transmitting session information and the content to a target base station during a handover of the terminal by using a logical interface between base stations in an LTE system, and in this case, a core cache function is additionally provided such that it is possible to smoothly provide the content to a base station even when moving to a server that does not have a cache function. Thus, backhaul costs caused by a handover are reduced and a user can be provided with improved quality of experience.

    SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

    公开(公告)号:US20240121963A1

    公开(公告)日:2024-04-11

    申请号:US18474307

    申请日:2023-09-26

    CPC classification number: H10B43/40 H10B43/27

    Abstract: A semiconductor memory device includes: a substrate including a first region and a second region, the first region includes a peripheral circuit and a first active region (FAR), and the second region includes memory cell blocks. The FAR includes a FAR first extension extending in a first direction, a FAR second extension extending in a second direction, and a FAR third extension extending in a third direction. The FAR first extension, the FAR second extension, and the FAR third extension form an angle greater than 90 degrees relative to one another. The device includes a first pass transistor circuit configured to transmit driving signals, and the first pass transistor circuit includes a FAR first gate structure on the FAR first extension, a FAR second gate structure on the FAR second extension, a FAR third gate structure on the FAR third extension, and a first shared source/drain.

    WALL MOUNT AND DISPLAY APPARATUS HAVING THE SAME

    公开(公告)号:US20210068543A1

    公开(公告)日:2021-03-11

    申请号:US16814516

    申请日:2020-03-10

    Abstract: A wall mount including a guide member. The guide member includes a first guide coupling portion positioned in one end portion of the guide member, a second guide coupling portion positioned in another end portion of the guide member, the second guide coupling portion being symmetrical to the first guide coupling portion, a third guide coupling portion positioned between the first guide coupling portion and a center of the guide member, and a fourth guide coupling portion positioned between the second guide coupling portion and the center of the guide member and being symmetrical to the third guide coupling portion; a first fixing bracket coupleable to the first guide coupling portion or the third guide coupling portion; and a second fixing bracket coupleable to the second guide coupling portion or the fourth guide coupling portion.

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请

    公开(公告)号:US20250126801A1

    公开(公告)日:2025-04-17

    申请号:US18732848

    申请日:2024-06-04

    Abstract: The present disclosure relates to semiconductor memory devices. An example semiconductor memory device includes a cell region and a peripheral circuit region electrically connected with the cell region. The cell region includes a plurality of gate electrodes spaced apart from each other and stacked in a vertical direction, and a channel structure extending through the plurality of gate electrodes in the vertical direction. The peripheral circuit region includes a substrate, a first element isolation structure, a first gate structure on the first active region, a second element isolation structure, a second gate structure on the second active region, a third element isolation structure, and a third gate structure on the third active region. The third element isolation structure includes a first element isolation pattern and a second element isolation pattern. The first element isolation pattern and the second element isolation pattern include different materials from each other.

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