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公开(公告)号：US09972636B2
公开(公告)日：2018-05-15
申请号：US15626395
申请日：2017-06-19
发明人： Jong Won Kim , Seung Hyun Lim , Chang Seok Kang , Young Woo Park , Dae Hoon Bae , Dong Seog Eun , Woo Sung Lee , Jae Duk Lee , Jae Woo Lim , Hanmei Choi
IPC分类号： H01L27/115 , H01L27/11565 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L27/1157 , H01L27/11582 , H01L27/11573 , H01L29/04
CPC分类号： H01L27/11565 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L28/00 , H01L29/04
摘要： A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
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公开(公告)号：US20240107770A1
公开(公告)日：2024-03-28
申请号：US18530049
申请日：2023-12-05
发明人： So Hyeon Lee , Sung Su Moon , Jae Duk Lee , Ik-Hyung Joo
摘要： A semiconductor memory device includes; a first stacked structure including a first staircase portion, a second stacked structure on the first stacked structure and including a second staircase portion overlapping the first staircase portion, a first contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the first stacked structure and not electrically connected to the second stacked structure, and a second contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the second stacked structure and not electrically connected to the first stacked structure.
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公开(公告)号：US11031410B2
公开(公告)日：2021-06-08
申请号：US16425365
申请日：2019-05-29
发明人： Se Jun Park , Min-Tai Yu , Jae Duk Lee
IPC分类号： H01L27/11556 , H01L27/11582 , G11C5/06
摘要： A nonvolatile memory device in which reliability is improved and a method for fabricating the same are provided. The nonvolatile memory device includes a mold structure which includes a first insulating pattern, a first gate electrode and a second insulating pattern sequentially stacked on a substrate, a semiconductor pattern which penetrates the mold structure, is connected to the substrate, and extends in a first direction, a first charge storage film extending in the first direction between the first insulating pattern and the second insulating pattern and between the first gate electrode and the semiconductor pattern, and a blocking insulation film between the first gate electrode and the first charge storage film, wherein a first length at which the first charge storage film extends in the first direction is longer than a second length at which the blocking insulation film extends in the first direction.
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公开(公告)号：US10192883B2
公开(公告)日：2019-01-29
申请号：US15863342
申请日：2018-01-05
发明人： Young Hwan Son , Young Woo Park , Jae Duk Lee
IPC分类号： H01L27/115 , G11C16/04 , H01L27/11582 , H01L27/11573 , G11C16/26 , G11C16/10 , H01L27/11565 , H01L27/1157 , H01L27/11575
摘要： A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer. The cell region may include a second substrate disposed on the first insulating layer, wherein the ceil region includes a first impurity region, a channel region extending in a direction substantially perpendicular to an upper surface of the second substrate, a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, and a first contact electrically connected to the first impurity region, wherein the first protective layer is disposed below the first impurity region, and has a shape corresponding to a shape of the first impurity region.
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公开(公告)号：US11881268B2
公开(公告)日：2024-01-23
申请号：US17712238
申请日：2022-04-04
发明人： Hye Ji Lee , Jin-Kyu Kang , Rae Young Lee , Se Jun Park , Jae Duk Lee , Gu Yeon Han
CPC分类号： G11C16/16 , G11C11/5635 , G11C11/5671 , G11C16/0483 , H10B41/27 , H10B43/27
摘要： A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.
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公开(公告)号：US11877450B2
公开(公告)日：2024-01-16
申请号：US17158494
申请日：2021-01-26
发明人： So Hyeon Lee , Sung Su Moon , Jae Duk Lee , Ik-Hyung Joo
摘要： A semiconductor memory device includes; a first stacked structure including a first staircase portion, a second stacked structure on the first stacked structure and including a second staircase portion overlapping the first staircase portion, a first contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the first stacked structure and not electrically connected to the second stacked structure, and a second contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the second stacked structure and not electrically connected to the first stacked structure.
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公开(公告)号：US10153292B2
公开(公告)日：2018-12-11
申请号：US15907667
申请日：2018-02-28
发明人： Jong Won Kim , Seung Hyun Lim , Chang Seok Kang , Young Woo Park , Dae Hoon Bae , Dong Seog Eun , Woo Sung Lee , Jae Duk Lee , Jae Woo Lim , Hanmei Choi
IPC分类号： H01L27/11556 , H01L27/11565 , H01L27/11582 , H01L27/11521 , H01L27/11568 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/1157 , H01L27/11573 , H01L29/04 , H01L49/02
摘要： A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
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公开(公告)号：US11574923B2
公开(公告)日：2023-02-07
申请号：US17152883
申请日：2021-01-20
发明人： Jang Gn Yun , Jae Duk Lee
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11556 , H01L27/11524
摘要： A three-dimensional semiconductor device includes a stacked structure on a lower structure, the stacked structure including a lower group including gate electrodes vertically stacked and spaced apart from each other, and an upper group including gate electrodes vertically stacked and spaced apart, the lower group and the upper group being vertically stacked, and a vertical structure passing through the stacked structure. The vertical structure may include a vertical core pattern, a vertical buffer portion therein, and a surrounding vertical semiconductor layer, the vertical structure may include a lower vertical portion passing through the lower group and an upper vertical portion passing through the upper group, an upper region of the lower vertical portion may have a width greater than that of a lower region of the upper vertical portion. The vertical buffer portion may be in the lower vertical portion and below the upper vertical portion.
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公开(公告)号：US20220013538A1
公开(公告)日：2022-01-13
申请号：US17158494
申请日：2021-01-26
发明人： So Hyeon Lee , Sung Su Moon , Jae Duk Lee , Ik-Hyung Joo
IPC分类号： H01L27/11582 , H01L23/522 , H01L27/11565 , H01L27/11573 , H01L27/11519 , H01L27/11556 , H01L27/11526
摘要： A semiconductor memory device includes; a first stacked structure including a first staircase portion, a second stacked structure on the first stacked structure and including a second staircase portion overlapping the first staircase portion, a first contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the first stacked structure and not electrically connected to the second stacked structure, and a second contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the second stacked structure and not electrically connected to the first stacked structure.
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公开(公告)号：US09716104B2
公开(公告)日：2017-07-25
申请号：US14987835
申请日：2016-01-05
发明人： Jong Won Kim , Seung Hyun Lim , Chang Seok Kang , Young Woo Park , Dae Hoon Bae , Dong Seog Eun , Woo Sung Lee , Jae Duk Lee , Jae Woo Lim , HanMei Choi
IPC分类号： H01L27/115 , H01L27/11582 , H01L27/11556 , H01L27/11521 , H01L27/11568
CPC分类号： H01L27/11565 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L28/00 , H01L29/04
摘要： A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
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