公开(公告)号：US10192883B2

公开(公告)日：2019-01-29

申请号：US15863342

申请日：2018-01-05

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Young Hwan Son ,  Young Woo Park ,  Jae Duk Lee

IPC分类号： H01L27/115 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

摘要： A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer. The cell region may include a second substrate disposed on the first insulating layer, wherein the ceil region includes a first impurity region, a channel region extending in a direction substantially perpendicular to an upper surface of the second substrate, a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, and a first contact electrically connected to the first impurity region, wherein the first protective layer is disposed below the first impurity region, and has a shape corresponding to a shape of the first impurity region.

公开(公告)号：US10153292B2

公开(公告)日：2018-12-11

申请号：US15907667

申请日：2018-02-28

申请人： Samsung Electronics Co., Ltd.

发明人： Jong Won Kim ,  Seung Hyun Lim ,  Chang Seok Kang ,  Young Woo Park ,  Dae Hoon Bae ,  Dong Seog Eun ,  Woo Sung Lee ,  Jae Duk Lee ,  Jae Woo Lim ,  Hanmei Choi

IPC分类号： H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/04 ,  H01L49/02

摘要： A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

公开(公告)号：US09893074B2

公开(公告)日：2018-02-13

申请号：US14662919

申请日：2015-03-19

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jae Goo Lee ,  Young Woo Park

IPC分类号： H01L29/792 ,  H01L29/788 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11575 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC分类号： H01L27/11556 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/4975 ,  H01L29/66666 ,  H01L29/7827

摘要： A semiconductor device including a substrate, channels, a gate stack, and a pad separating region. The substrate has a pad region adjacent to a cell region. The channels extend in a direction crossing an upper surface of the substrate in the cell region. The gate stack includes a plurality of gate electrode layers spaced apart from each other on the substrate and enclosing the channels in the cell region. The pad separating region separates the gate stack into two or more regions in the pad region. The gate electrode layers have different lengths in the pad region.

公开(公告)号：US09716104B2

公开(公告)日：2017-07-25

申请号：US14987835

申请日：2016-01-05

申请人： Samsung Electronics Co., Ltd.

发明人： Jong Won Kim ,  Seung Hyun Lim ,  Chang Seok Kang ,  Young Woo Park ,  Dae Hoon Bae ,  Dong Seog Eun ,  Woo Sung Lee ,  Jae Duk Lee ,  Jae Woo Lim ,  HanMei Choi

IPC分类号： H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11521 ,  H01L27/11568

CPC分类号： H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04

摘要： A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

公开(公告)号：US20150132906A1

公开(公告)日：2015-05-14

申请号：US14599621

申请日：2015-01-19

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sung-Il Chang ,  Young Woo Park ,  Jae Goo Lee

IPC分类号： H01L27/115 ,  H01L21/311

CPC分类号： H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/42324 ,  H01L29/4234

摘要： A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.

公开(公告)号：US09972636B2

公开(公告)日：2018-05-15

申请号：US15626395

申请日：2017-06-19

申请人： Samsung Electronics Co., Ltd.

发明人： Jong Won Kim ,  Seung Hyun Lim ,  Chang Seok Kang ,  Young Woo Park ,  Dae Hoon Bae ,  Dong Seog Eun ,  Woo Sung Lee ,  Jae Duk Lee ,  Jae Woo Lim ,  Hanmei Choi

IPC分类号： H01L27/115 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/04

CPC分类号： H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04

摘要： A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.