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公开(公告)号：US12225725B2
公开(公告)日：2025-02-11
申请号：US17650700
申请日：2022-02-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： So Hyeon Lee
IPC: H01L23/52 , H01L23/522 , H01L23/528 , H01L29/417 , H01L29/423 , H10B41/27 , H10B41/30 , H10B43/27 , H10B43/30 , H01L21/02 , H01L21/28 , H01L21/311 , H01L21/3115 , H01L21/768 , H01L29/66 , H01L29/788
Abstract: A semiconductor device includes a vertical stack of gate electrodes. The gate electrodes extend in different lengths to provide contact regions. The gate electrodes have a conductive region and an insulating region. Contact plugs fills contact holes that pass through the stack of gate electrodes in the contact regions. The contact plugs are connected to the gate electrodes. The contact plugs pass through a conductive region of one gate electrode and are electrically connected to the one gate electrode and pass through the insulating region of other gate electrodes in the contact region. The insulating region is disposed outside of the contact holes in a region in which the gate electrodes intersect the contact plugs.
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Patent Agency Ranking
公开(公告)号：US20240107770A1
公开(公告)日：2024-03-28
申请号：US18530049
申请日：2023-12-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： So Hyeon Lee , Sung Su Moon , Jae Duk Lee , Ik-Hyung Joo
CPC classification number: H10B43/27 , H01L23/5226 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/40
Abstract: A semiconductor memory device includes; a first stacked structure including a first staircase portion, a second stacked structure on the first stacked structure and including a second staircase portion overlapping the first staircase portion, a first contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the first stacked structure and not electrically connected to the second stacked structure, and a second contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the second stacked structure and not electrically connected to the first stacked structure.
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公开(公告)号：US11877450B2
公开(公告)日：2024-01-16
申请号：US17158494
申请日：2021-01-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： So Hyeon Lee , Sung Su Moon , Jae Duk Lee , Ik-Hyung Joo
CPC classification number: H10B43/27 , H01L23/5226 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/40
Abstract: A semiconductor memory device includes; a first stacked structure including a first staircase portion, a second stacked structure on the first stacked structure and including a second staircase portion overlapping the first staircase portion, a first contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the first stacked structure and not electrically connected to the second stacked structure, and a second contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the second stacked structure and not electrically connected to the first stacked structure.
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公开(公告)号：US20220013538A1
公开(公告)日：2022-01-13
申请号：US17158494
申请日：2021-01-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： So Hyeon Lee , Sung Su Moon , Jae Duk Lee , Ik-Hyung Joo
IPC: H01L27/11582 , H01L23/522 , H01L27/11565 , H01L27/11573 , H01L27/11519 , H01L27/11556 , H01L27/11526
Abstract: A semiconductor memory device includes; a first stacked structure including a first staircase portion, a second stacked structure on the first stacked structure and including a second staircase portion overlapping the first staircase portion, a first contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the first stacked structure and not electrically connected to the second stacked structure, and a second contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the second stacked structure and not electrically connected to the first stacked structure.
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公开(公告)号：US12302572B2
公开(公告)日：2025-05-13
申请号：US18530049
申请日：2023-12-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： So Hyeon Lee , Sung Su Moon , Jae Duk Lee , Ik-Hyung Joo
Abstract: A semiconductor memory device includes; a first stacked structure including a first staircase portion, a second stacked structure on the first stacked structure and including a second staircase portion overlapping the first staircase portion, a first contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the first stacked structure and not electrically connected to the second stacked structure, and a second contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the second stacked structure and not electrically connected to the first stacked structure.
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公开(公告)号：US11251192B2
公开(公告)日：2022-02-15
申请号：US16386740
申请日：2019-04-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： So Hyeon Lee
IPC: H01L27/11 , H01L27/11582 , H01L23/522 , H01L29/417 , H01L27/11521 , H01L27/11556 , H01L27/11568 , H01L29/423 , H01L23/528 , H01L21/768 , H01L29/788 , H01L29/66 , H01L21/3115 , H01L21/311 , H01L21/02 , H01L21/28
Abstract: A semiconductor device includes a vertical stack of gate electrodes. The gate electrodes extend in different lengths to provide contact regions. The gate electrodes have a conductive region and an insulating region. Contact plugs fills contact holes that pass through the stack of gate electrodes in the contact regions. The contact plugs are connected to the gate electrodes. The contact plugs pass through a conductive region of one gate electrode and are electrically connected to the one gate electrode and pass through the insulating region of other gate electrodes in the contact region. The insulating region is disposed outside of the contact holes in a region in which the gate electrodes intersect the contact plugs.
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