-
公开(公告)号：US11791846B2
公开(公告)日：2023-10-17
申请号：US17314768
申请日：2021-05-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae Hun Jang , Dong-Min Shin , Heon Hwa Cheong , Jun Jin Kong , Hong Rak Son , Se Jin Lim
CPC classification number: H03M13/37 , G06F11/085 , G06F11/1012 , G06F13/1673 , H03M13/03
Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.
-
公开(公告)号：US12200106B2
公开(公告)日：2025-01-14
申请号：US17698639
申请日：2022-03-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae Hun Jang , Ji Youp Kim , Han Byeul Na , Young Suk Ra , Man Keun Seo , Hong Rak Son , Se Jin Lim
Abstract: A memory device includes an input unit configured to receive a plain text and output plain blocks and CTS plain block, a multi-core unit including a plurality of encryption/decryption cores configured to encrypt each of the plain blocks provided from the input unit and output cipher blocks in accordance with control of an encryption/decryption core control unit, a CTS core unit including a CTS core configured to encrypt the CTS plain block provided from the input unit into a CTS cipher block, and an output unit configured to receive the cipher blocks and the CTS cipher block and output a cipher text. The CTS plain block is generated through a CTS calculation based on the plain text.
-
公开(公告)号：US20250112760A1
公开(公告)日：2025-04-03
申请号：US18979286
申请日：2024-12-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae Hun Jang , Ji Youp Kim , Han Byeul Na , Young Suk Ra , Man Keun Seo , Hong Rak Son , Se Jin Lim
Abstract: A memory device includes an input unit configured to receive a plain text and output plain blocks and CTS plain block, a multi-core unit including a plurality of encryption/decryption cores configured to encrypt each of the plain blocks provided from the input unit and output cipher blocks in accordance with control of an encryption/decryption core control unit, a CTS core unit including a CTS core configured to encrypt the CTS plain block provided from the input unit into a CTS cipher block, and an output unit configured to receive the cipher blocks and the CTS cipher block and output a cipher text. The CTS plain block is generated through a CTS calculation based on the plain text.
-
Patent Agency Ranking
公开(公告)号：US11128321B2
公开(公告)日：2021-09-21
申请号：US16882627
申请日：2020-05-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong Min Shin , Beom Kyu Shin , Heon Hwa Cheong , Jun Jin Kong , Hong Rak Son , Yeong Geol Song , Se Jin Lim
Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.
-
公开(公告)号：US20250126801A1
公开(公告)日：2025-04-17
申请号：US18732848
申请日：2024-06-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ju Seong Min , Hak Seon Kim , Jae-Bok Baek , Kang-Oh Yun , Taek Kyu Yoon , Dong Jin Lee , Jae Duk Lee , Se Jin Lim , Jee Hoon Han
Abstract: The present disclosure relates to semiconductor memory devices. An example semiconductor memory device includes a cell region and a peripheral circuit region electrically connected with the cell region. The cell region includes a plurality of gate electrodes spaced apart from each other and stacked in a vertical direction, and a channel structure extending through the plurality of gate electrodes in the vertical direction. The peripheral circuit region includes a substrate, a first element isolation structure, a first gate structure on the first active region, a second element isolation structure, a second gate structure on the second active region, a third element isolation structure, and a third gate structure on the third active region. The third element isolation structure includes a first element isolation pattern and a second element isolation pattern. The first element isolation pattern and the second element isolation pattern include different materials from each other.
-
公开(公告)号：US10700714B2
公开(公告)日：2020-06-30
申请号：US16229153
申请日：2018-12-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong Min Shin , Beom Kyu Shin , Heon Hwa Cheong , Jun Jin Kong , Hong Rak Son , Yeong Geol Song , Se Jin Lim
Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.
-
公开(公告)号：US11031957B2
公开(公告)日：2021-06-08
申请号：US15956960
申请日：2018-04-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae Hun Jang , Dong-Min Shin , Heon Hwa Cheong , Jun Jin Kong , Hong Rak Son , Se Jin Lim
Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.
-
公开(公告)号：US10164663B2
公开(公告)日：2018-12-25
申请号：US15613659
申请日：2017-06-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong Min Shin , Beom Kyu Shin , Heon Hwa Cheong , Jun Jin Kong , Hong Rak Son , Yeong Geol Song , Se Jin Lim
Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.015 seconds)
